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Searched refs:FIQ_REG (Results 1 – 25 of 34) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/mbx/hal/k6/mbx/
H A DhalMBXINT.c325 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
326 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
333 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
334 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
345 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
346 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
354 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
355 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
365 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63)); in MHAL_MBXINT_Fire()
366 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63)); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h121 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/curry/mbx/
H A DhalMBXINT.c325 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
326 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
333 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
334 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
345 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
346 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
354 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
355 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
365 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63)); in MHAL_MBXINT_Fire()
366 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63)); in MHAL_MBXINT_Fire()
[all …]
/utopia/UTPA2-700.0.x/modules/mbx/hal/k6lite/mbx/
H A DhalMBXINT.c325 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
326 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
333 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
334 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
345 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
346 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
354 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
355 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
365 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63)); in MHAL_MBXINT_Fire()
366 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63)); in MHAL_MBXINT_Fire()
[all …]
/utopia/UTPA2-700.0.x/modules/mbx/hal/kano/mbx/
H A DhalMBXINT.c325 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
326 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
333 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
334 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
345 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
346 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
354 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
355 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
365 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63)); in MHAL_MBXINT_Fire()
366 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63)); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h121 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mooney/mbx/
H A DhalMBXINT.c322 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
323 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
331 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
332 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
345 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
346 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
354 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
355 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
368 MBXINT_PRINT("FIQ [48-63] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63)); in MHAL_MBXINT_Fire()
369 MBXINT_PRINT("FIQ [48-63] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63)); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h101 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/maldives/mbx/
H A DhalMBXINT.c320 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
321 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
329 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
330 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
343 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
344 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
352 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
353 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
366 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
367 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h101 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/macan/mbx/
H A DhalMBXINT.c324 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
325 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
332 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
333 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
344 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
345 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
353 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
354 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
364 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63)); in MHAL_MBXINT_Fire()
365 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63)); in MHAL_MBXINT_Fire()
[all …]
/utopia/UTPA2-700.0.x/modules/mbx/hal/messi/mbx/
H A DhalMBXINT.c324 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
325 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
333 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
334 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
347 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
348 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
356 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
357 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
370 MBXINT_PRINT("FIQ [48-63] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63)); in MHAL_MBXINT_Fire()
371 MBXINT_PRINT("FIQ [48-63] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63)); in MHAL_MBXINT_Fire()
[all …]
/utopia/UTPA2-700.0.x/modules/mbx/hal/mustang/mbx/
H A DhalMBXINT.c320 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
321 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
329 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
330 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
343 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
344 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
352 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
353 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
366 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
367 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h101 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mainz/mbx/
H A DhalMBXINT.c324 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
325 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
333 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
334 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
347 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
348 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
356 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
357 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
370 MBXINT_PRINT("FIQ [48-63] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63)); in MHAL_MBXINT_Fire()
371 MBXINT_PRINT("FIQ [48-63] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63)); in MHAL_MBXINT_Fire()
[all …]
H A DregMBXINT.h101 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE] macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7821/mbx/
H A DhalMBXINT.c377 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
378 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
385 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
386 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
397 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
398 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
406 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
407 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
417 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63)); in MHAL_MBXINT_Fire()
418 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63)); in MHAL_MBXINT_Fire()
[all …]
/utopia/UTPA2-700.0.x/modules/mbx/hal/manhattan/mbx/
H A DhalMBXINT.c377 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
378 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
385 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
386 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
397 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
398 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
406 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
407 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
417 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63)); in MHAL_MBXINT_Fire()
418 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63)); in MHAL_MBXINT_Fire()
[all …]
/utopia/UTPA2-700.0.x/modules/mbx/hal/maxim/mbx/
H A DhalMBXINT.c377 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
378 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
385 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
386 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
397 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
398 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
406 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
407 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
417 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63)); in MHAL_MBXINT_Fire()
418 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63)); in MHAL_MBXINT_Fire()
[all …]
/utopia/UTPA2-700.0.x/modules/mbx/hal/maserati/mbx/
H A DhalMBXINT.c377 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
378 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
385 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
386 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
397 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
398 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
406 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
407 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
417 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63)); in MHAL_MBXINT_Fire()
418 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63)); in MHAL_MBXINT_Fire()
[all …]
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7621/mbx/
H A DhalMBXINT.c377 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
378 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
385 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
386 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
397 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
398 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
406 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47)); in MHAL_MBXINT_Fire()
407 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47)); in MHAL_MBXINT_Fire()
417 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63)); in MHAL_MBXINT_Fire()
418 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63)); in MHAL_MBXINT_Fire()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/fq/
H A DhalFQ.c114 #define FIQ_REG(addr) (*((volatile MS_U16*)(_virtRegBase + FQ_REG_CTRL_BASE + ((addr)<… macro
355 _u16FQRegArray[0][u32ii] = FIQ_REG(u32ii); in HAL_FQ_SaveRegs()
380 FIQ_REG(0)= (_u16FQRegArray[0][0] | FIQ_CFG0_RUSH_ENABLE) & ~FIQ_CFG0_PVR_ENABLE; in HAL_FQ_RestoreRegs()
383 FIQ_REG(u32ii)= _u16FQRegArray[0][u32ii]; in HAL_FQ_RestoreRegs()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/fq/
H A DhalFQ.c114 #define FIQ_REG(addr) (*((volatile MS_U16*)(_virtRegBase + FQ_REG_CTRL_BASE + ((addr)<… macro
355 _u16FQRegArray[0][u32ii] = FIQ_REG(u32ii); in HAL_FQ_SaveRegs()
380 FIQ_REG(0)= (_u16FQRegArray[0][0] | FIQ_CFG0_RUSH_ENABLE) & ~FIQ_CFG0_PVR_ENABLE; in HAL_FQ_RestoreRegs()
383 FIQ_REG(u32ii)= _u16FQRegArray[0][u32ii]; in HAL_FQ_RestoreRegs()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/fq/
H A DhalFQ.c115 #define FIQ_REG(addr) (*((volatile MS_U16*)(_virtRegBase + FQ_REG_CTRL_BASE + ((addr)<… macro
355 _u16FQRegArray[0][u32ii] = FIQ_REG(u32ii); in HAL_FQ_SaveRegs()
380 FIQ_REG(0)= (_u16FQRegArray[0][0] | FIQ_CFG0_RUSH_ENABLE) & ~FIQ_CFG0_PVR_ENABLE; in HAL_FQ_RestoreRegs()
383 FIQ_REG(u32ii)= _u16FQRegArray[0][u32ii]; in HAL_FQ_RestoreRegs()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/fq/
H A DhalFQ.c115 #define FIQ_REG(addr) (*((volatile MS_U16*)(_virtRegBase + FQ_REG_CTRL_BASE + ((addr)<… macro
355 _u16FQRegArray[0][u32ii] = FIQ_REG(u32ii); in HAL_FQ_SaveRegs()
380 FIQ_REG(0)= (_u16FQRegArray[0][0] | FIQ_CFG0_RUSH_ENABLE) & ~FIQ_CFG0_PVR_ENABLE; in HAL_FQ_RestoreRegs()
383 FIQ_REG(u32ii)= _u16FQRegArray[0][u32ii]; in HAL_FQ_RestoreRegs()

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