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Searched refs:CLKGEN1_REG_BASE (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6lite/hwi2c/
H A DregHWI2C.h113 #define CLKGEN1_REG_BASE (0x3300) macro
141 #define CHIP_REG_HWI2C_MIIC0_CLK (CLKGEN1_REG_BASE + (0x30) * 2)
148 #define CHIP_REG_HWI2C_MIIC1_CLK (CLKGEN1_REG_BASE + (0x30) * 2)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/kano/hwi2c/
H A DregHWI2C.h113 #define CLKGEN1_REG_BASE (0x3300) macro
141 #define CHIP_REG_HWI2C_MIIC0_CLK (CLKGEN1_REG_BASE + (0x30) * 2)
148 #define CHIP_REG_HWI2C_MIIC1_CLK (CLKGEN1_REG_BASE + (0x30) * 2)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6/hwi2c/
H A DregHWI2C.h113 #define CLKGEN1_REG_BASE (0x3300) macro
141 #define CHIP_REG_HWI2C_MIIC0_CLK (CLKGEN1_REG_BASE + (0x30) * 2)
148 #define CHIP_REG_HWI2C_MIIC1_CLK (CLKGEN1_REG_BASE + (0x30) * 2)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/curry/hwi2c/
H A DregHWI2C.h113 #define CLKGEN1_REG_BASE (0x3300) macro
141 #define CHIP_REG_HWI2C_MIIC0_CLK (CLKGEN1_REG_BASE + (0x30) * 2)
148 #define CHIP_REG_HWI2C_MIIC1_CLK (CLKGEN1_REG_BASE + (0x30) * 2)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DregVPU_EX.h385 #define CLKGEN1_REG_BASE (0x3300) macro
397 #define REG_CLKGEN1_RESERVERD0 (CLKGEN1_REG_BASE+(0x003e<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h385 #define CLKGEN1_REG_BASE (0x3300) macro
397 #define REG_CLKGEN1_RESERVERD0 (CLKGEN1_REG_BASE+(0x003e<<1))
/utopia/UTPA2-700.0.x/modules/mvop/hal/kastor/mvop/
H A DregMVOP.h115 #define CLKGEN1_REG_BASE 0x3300 //chiptop CLKGEN01 macro
479 #define REG_CKG_FBDEC (CLKGEN1_REG_BASE + 0x4A)
/utopia/UTPA2-700.0.x/modules/mvop/hal/k6lite/mvop/
H A DregMVOP.h115 #define CLKGEN1_REG_BASE 0x3300 //chiptop CLKGEN01 macro
489 #define REG_CKG_FBDEC (CLKGEN1_REG_BASE + 0x4A)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DregVPU_EX.h385 #define CLKGEN1_REG_BASE (0x3300) macro
397 #define REG_CLKGEN1_RESERVERD0 (CLKGEN1_REG_BASE+(0x003e<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h385 #define CLKGEN1_REG_BASE (0x3300) macro
397 #define REG_CLKGEN1_RESERVERD0 (CLKGEN1_REG_BASE+(0x003e<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A DregVPU_EX.h385 #define CLKGEN1_REG_BASE (0x3300) macro
397 #define REG_CLKGEN1_RESERVERD0 (CLKGEN1_REG_BASE+(0x003e<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A DregVPU_EX.h385 #define CLKGEN1_REG_BASE (0x3300) macro
397 #define REG_CLKGEN1_RESERVERD0 (CLKGEN1_REG_BASE+(0x003e<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A DregVPU_EX.h385 #define CLKGEN1_REG_BASE (0x3300) macro
397 #define REG_CLKGEN1_RESERVERD0 (CLKGEN1_REG_BASE+(0x003e<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A DregVPU_EX.h385 #define CLKGEN1_REG_BASE (0x3300) macro
397 #define REG_CLKGEN1_RESERVERD0 (CLKGEN1_REG_BASE+(0x003e<<1))
/utopia/UTPA2-700.0.x/modules/mvop/hal/k6/mvop/
H A DregMVOP.h115 #define CLKGEN1_REG_BASE 0x3300 //chiptop CLKGEN01 macro
545 #define REG_CKG_FBDEC (CLKGEN1_REG_BASE + 0x4A)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/
H A DhalHDMITx.c771 MHal_HDMITx_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, 0); // enable clk_hdmi_tx_p in MHal_HDMITx_InitSeq()
1989 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, 0); in MHal_HDMITx_Power_OnOff()
1993 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, BIT0); in MHal_HDMITx_Power_OnOff()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/
H A DhalHDMITx.c798 MHal_HDMITx_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, 0); // enable clk_hdmi_tx_p in MHal_HDMITx_InitSeq()
1988 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, 0); in MHal_HDMITx_Power_OnOff()
1992 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, BIT0); in MHal_HDMITx_Power_OnOff()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/
H A DhalHDMITx.c820 MHal_HDMITx_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, 0); // enable clk_hdmi_tx_p in MHal_HDMITx_InitSeq()
2074 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, 0); in MHal_HDMITx_Power_OnOff()
2078 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, BIT0); in MHal_HDMITx_Power_OnOff()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/include/
H A DregHDMITx.h132 #define CLKGEN1_REG_BASE (0x103300U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/include/
H A DregHDMITx.h132 #define CLKGEN1_REG_BASE (0x103300U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/include/
H A DregHDMITx.h132 #define CLKGEN1_REG_BASE (0x103300U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/include/
H A DregHDMITx.h132 #define CLKGEN1_REG_BASE (0x103300U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/include/
H A DregHDMITx.h131 #define CLKGEN1_REG_BASE (0x103300U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/include/
H A DregHDMITx.h131 #define CLKGEN1_REG_BASE (0x103300U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/
H A DhalHDMITx.c808 MHal_HDMITx_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, 0); // enable clk_hdmi_tx_p in MHal_HDMITx_InitSeq()
2020 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, 0); in MHal_HDMITx_Power_OnOff()
2024 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, BIT0); in MHal_HDMITx_Power_OnOff()

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