1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 //////////////////////////////////////////////////////////////////////////////// 93 94 #ifndef _REGHWI2C_H_ 95 #define _REGHWI2C_H_ 96 97 //////////////////////////////////////////////////////////////////////////////// 98 // Header Files 99 //////////////////////////////////////////////////////////////////////////////// 100 101 //////////////////////////////////////////////////////////////////////////////// 102 // Define & data type 103 //////////////////////////////////////////////////////////////////////////////// 104 105 //############################ 106 // 107 //IP bank address : for pad mux in chiptop 108 // 109 //############################ 110 #define CHIP_REG_BASE (0x1E00) 111 #define PIU_NONPM_REG_BASE (0x3C00) //0x103C_02_Bit[1:0] 112 #define PMSLEEP_REG_BASE (0x0E00) 113 #define CLKGEN1_REG_BASE (0x3300) 114 //for port 0 115 116 #define CHIP_REG_HWI2C_MIIC0 (CHIP_REG_BASE+ (0x09*2)) 117 #define CHIP_MIIC0_PAD_0 0 118 #define CHIP_MIIC0_PAD_1 (__BIT0) 119 #define CHIP_MIIC0_PAD_2 (__BIT1) 120 #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1) 121 #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1) 122 123 //for port 1 124 #define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x09*2)) 125 #define CHIP_MIIC1_PAD_0 (0) 126 #define CHIP_MIIC1_PAD_1 (__BIT2) 127 #define CHIP_MIIC1_PAD_2 (__BIT3) 128 #define CHIP_MIIC1_PAD_3 (__BIT2|__BIT3) 129 #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3) 130 131 132 //pad mux configuration 133 #define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA1) 134 #define CHIP_ALLPAD_IN (__BIT7) 135 136 #define REG_HWI2C_MIIC_VER_SEL (PIU_NONPM_REG_BASE+ (0x02*2)) //select MI2C mode 137 #define REG_HWI2C_MIIC_VER_V2 (0) 138 #define REG_HWI2C_MIIC_VER_V3 (__BIT1|__BIT0) 139 #define REG_HWI2C_MIIC_VER_MSK (__BIT1|__BIT0) 140 141 #define CHIP_REG_HWI2C_MIIC0_CLK (CLKGEN1_REG_BASE + (0x30) * 2) 142 #define CHIP_REG_HWI2C_MIIC0_CLK_72M 0 143 #define CHIP_REG_HWI2C_MIIC0_CLK_XTAL (__BIT2) 144 #define CHIP_REG_HWI2C_MIIC0_CLL_36M (__BIT3) 145 #define CHIP_REG_HWI2C_MIIC0_CLK_54M (__BIT2 | __BIT3) 146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3) 147 148 #define CHIP_REG_HWI2C_MIIC1_CLK (CLKGEN1_REG_BASE + (0x30) * 2) 149 #define CHIP_REG_HWI2C_MIIC1_CLK_72M 0 150 #define CHIP_REG_HWI2C_MIIC1_CLK_XTAL (__BIT6) 151 #define CHIP_REG_HWI2C_MIIC1_CLL_36M (__BIT7) 152 #define CHIP_REG_HWI2C_MIIC1_CLK_54M (__BIT6 | __BIT7) 153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7) 154 //############################ 155 // 156 //IP bank address : for independent port 157 // 158 //############################ 159 //Standard mode 160 #define HWI2C_REG_BASE (0x13400) //0x1(13400) + offset ==> default set to port 0 161 #define HWI2C_REG_BASE_PM (0x01700) //port3 in PM bank 162 163 //################# 164 //# 165 //# For Non-PM HWI2C 166 //# 167 //STD mode 168 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2) 169 #define _MIIC_CFG_RESET (__BIT0) 170 #define _MIIC_CFG_EN_DMA (__BIT1) 171 #define _MIIC_CFG_EN_INT (__BIT2) 172 #define _MIIC_CFG_EN_CLKSTR (__BIT3) 173 #define _MIIC_CFG_EN_TMTINT (__BIT4) 174 #define _MIIC_CFG_EN_FILTER (__BIT5) 175 #define _MIIC_CFG_EN_PUSH1T (__BIT6) 176 #define _MIIC_CFG_RESERVED (__BIT7) 177 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2) 178 #define _CMD_START (__BIT0) 179 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1) 180 #define _CMD_STOP (__BIT0) 181 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2) 182 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1) 183 #define _WDATA_GET_ACKBIT (__BIT0) 184 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2) 185 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1) 186 #define _RDATA_CFG_TRIG (__BIT0) 187 #define _RDATA_CFG_ACKBIT (__BIT1) 188 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) 189 #define _INT_CTL (__BIT0) //write this register to clear int 190 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug 191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) 192 #define REG_HWI2C_INT_STATUS (HWI2C_REG_BASE+0x05*2+1) //For Debug 193 #define _INT_STARTDET (__BIT0) 194 #define _INT_STOPDET (__BIT1) 195 #define _INT_RXDONE (__BIT2) 196 #define _INT_TXDONE (__BIT3) 197 #define _INT_CLKSTR (__BIT4) 198 #define _INT_SCLERR (__BIT5) 199 #define REG_HWI2C_STP_CNT (HWI2C_REG_BASE+0x08*2) 200 #define REG_HWI2C_CKH_CNT (HWI2C_REG_BASE+0x09*2) 201 #define REG_HWI2C_CKL_CNT (HWI2C_REG_BASE+0x0A*2) 202 #define REG_HWI2C_SDA_CNT (HWI2C_REG_BASE+0x0B*2) 203 #define REG_HWI2C_STT_CNT (HWI2C_REG_BASE+0x0C*2) 204 #define REG_HWI2C_LTH_CNT (HWI2C_REG_BASE+0x0D*2) 205 #define REG_HWI2C_TMT_CNT (HWI2C_REG_BASE+0x0E*2) 206 #define REG_HWI2C_SCLI_DELAY (HWI2C_REG_BASE+0x0F*2) 207 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) 208 209 //DMA mode 210 #define REG_HWI2C_DMA_CFG (HWI2C_REG_BASE+0x20*2) 211 #define _DMA_CFG_RESET (__BIT1) 212 #define _DMA_CFG_INTEN (__BIT2) 213 #define _DMA_CFG_MIURST (__BIT3) 214 #define _DMA_CFG_MIUPRI (__BIT4) 215 #define REG_HWI2C_DMA_MIU_ADR (HWI2C_REG_BASE+0x21*2) // 4 bytes 216 #define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) 217 // #define _DMA_CTL_TRIG (__BIT0) 218 // #define _DMA_CTL_RETRIG (__BIT1) 219 #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P 220 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write 221 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 222 #define REG_HWI2C_DMA_TXR (HWI2C_REG_BASE+0x24*2) 223 #define _DMA_TXR_DONE (__BIT0) 224 #define REG_HWI2C_DMA_CMDDAT0 (HWI2C_REG_BASE+0x25*2) // 8 bytes 225 #define REG_HWI2C_DMA_CMDDAT1 (HWI2C_REG_BASE+0x25*2+1) 226 #define REG_HWI2C_DMA_CMDDAT2 (HWI2C_REG_BASE+0x26*2) 227 #define REG_HWI2C_DMA_CMDDAT3 (HWI2C_REG_BASE+0x26*2+1) 228 #define REG_HWI2C_DMA_CMDDAT4 (HWI2C_REG_BASE+0x27*2) 229 #define REG_HWI2C_DMA_CMDDAT5 (HWI2C_REG_BASE+0x27*2+1) 230 #define REG_HWI2C_DMA_CMDDAT6 (HWI2C_REG_BASE+0x28*2) 231 #define REG_HWI2C_DMA_CMDDAT7 (HWI2C_REG_BASE+0x28*2+1) 232 #define REG_HWI2C_DMA_CMDLEN (HWI2C_REG_BASE+0x29*2) 233 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) 234 #define REG_HWI2C_DMA_DATLEN (HWI2C_REG_BASE+0x2A*2) // 4 bytes 235 #define REG_HWI2C_DMA_TXFRCNT (HWI2C_REG_BASE+0x2C*2) // 4 bytes 236 #define REG_HWI2C_DMA_SLVADR (HWI2C_REG_BASE+0x2E*2) 237 #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits 238 #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits 239 #define REG_HWI2C_DMA_SLVCFG (HWI2C_REG_BASE+0x2E*2+1) 240 #define _DMA_10BIT_MODE (__BIT2) 241 #define REG_HWI2C_DMA_CTL_TRIG (HWI2C_REG_BASE+0x2F*2) 242 #define _DMA_CTL_TRIG (__BIT0) 243 #define REG_HWI2C_DMA_CTL_RETRIG (HWI2C_REG_BASE+0x2F*2+1) 244 #define _DMA_CTL_RETRIG (__BIT0) 245 246 //################# 247 //# 248 //# For PM HWI2C 249 //# 250 //STD mode 251 #define REG_HWI2C_MIIC_CFG_PM (HWI2C_REG_BASE_PM+0x00*2) 252 #define _MIIC_CFG_RESET (__BIT0) 253 #define _MIIC_CFG_EN_DMA (__BIT1) 254 #define _MIIC_CFG_EN_INT (__BIT2) 255 #define _MIIC_CFG_EN_CLKSTR (__BIT3) 256 #define _MIIC_CFG_EN_TMTINT (__BIT4) 257 #define _MIIC_CFG_EN_FILTER (__BIT5) 258 #define _MIIC_CFG_EN_PUSH1T (__BIT6) 259 #define _MIIC_CFG_RESERVED (__BIT7) 260 #define REG_HWI2C_CMD_START_PM (HWI2C_REG_BASE_PM+0x01*2) 261 #define _CMD_START (__BIT0) 262 #define REG_HWI2C_CMD_STOP_PM (HWI2C_REG_BASE_PM+0x01*2+1) 263 #define _CMD_STOP (__BIT0) 264 #define REG_HWI2C_WDATA_PM (HWI2C_REG_BASE_PM+0x02*2) 265 #define REG_HWI2C_WDATA_GET_PM (HWI2C_REG_BASE_PM+0x02*2+1) 266 #define _WDATA_GET_ACKBIT (__BIT0) 267 #define REG_HWI2C_RDATA_PM (HWI2C_REG_BASE_PM+0x03*2) 268 #define REG_HWI2C_RDATA_CFG_PM (HWI2C_REG_BASE_PM+0x03*2+1) 269 #define _RDATA_CFG_TRIG (__BIT0) 270 #define _RDATA_CFG_ACKBIT (__BIT1) 271 #define REG_HWI2C_INT_CTL_PM (HWI2C_REG_BASE_PM+0x04*2) 272 #define _INT_CTL (__BIT0) //write this register to clear int 273 #define REG_HWI2C_CUR_STATE_PM (HWI2C_REG_BASE_PM+0x05*2) //For Debug 274 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) 275 #define REG_HWI2C_INT_STATUS_PM (HWI2C_REG_BASE_PM+0x05*2+1) //For Debug 276 #define _INT_STARTDET (__BIT0) 277 #define _INT_STOPDET (__BIT1) 278 #define _INT_RXDONE (__BIT2) 279 #define _INT_TXDONE (__BIT3) 280 #define _INT_CLKSTR (__BIT4) 281 #define _INT_SCLERR (__BIT5) 282 #define REG_HWI2C_STP_CNT_PM (HWI2C_REG_BASE_PM+0x08*2) 283 #define REG_HWI2C_CKH_CNT_PM (HWI2C_REG_BASE_PM+0x09*2) 284 #define REG_HWI2C_CKL_CNT_PM (HWI2C_REG_BASE_PM+0x0A*2) 285 #define REG_HWI2C_SDA_CNT_PM (HWI2C_REG_BASE_PM+0x0B*2) 286 #define REG_HWI2C_STT_CNT_PM (HWI2C_REG_BASE_PM+0x0C*2) 287 #define REG_HWI2C_LTH_CNT_PM (HWI2C_REG_BASE_PM+0x0D*2) 288 #define REG_HWI2C_TMT_CNT_PM (HWI2C_REG_BASE_PM+0x0E*2) 289 #define REG_HWI2C_SCLI_DELAY_PM (HWI2C_REG_BASE_PM+0x0F*2) 290 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) 291 292 //DMA mode 293 #define REG_HWI2C_DMA_CFG_PM (HWI2C_REG_BASE_PM+0x20*2) 294 #define _DMA_CFG_RESET (__BIT1) 295 #define _DMA_CFG_INTEN (__BIT2) 296 #define _DMA_CFG_MIURST (__BIT3) 297 #define _DMA_CFG_MIUPRI (__BIT4) 298 #define REG_HWI2C_DMA_MIU_ADR_PM (HWI2C_REG_BASE_PM+0x21*2) // 4 bytes 299 #define REG_HWI2C_DMA_CTL_PM (HWI2C_REG_BASE_PM+0x23*2) 300 // #define _DMA_CTL_TRIG (__BIT0) 301 // #define _DMA_CTL_RETRIG (__BIT1) 302 #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P 303 #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write 304 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 305 #define REG_HWI2C_DMA_TXR_PM (HWI2C_REG_BASE_PM+0x24*2) 306 #define _DMA_TXR_DONE (__BIT0) 307 #define REG_HWI2C_DMA_CMDDAT0_PM (HWI2C_REG_BASE_PM+0x25*2) // 8 bytes 308 #define REG_HWI2C_DMA_CMDDAT1_PM (HWI2C_REG_BASE_PM+0x25*2+1) 309 #define REG_HWI2C_DMA_CMDDAT2_PM (HWI2C_REG_BASE_PM+0x26*2) 310 #define REG_HWI2C_DMA_CMDDAT3_PM (HWI2C_REG_BASE_PM+0x26*2+1) 311 #define REG_HWI2C_DMA_CMDDAT4_PM (HWI2C_REG_BASE_PM+0x27*2) 312 #define REG_HWI2C_DMA_CMDDAT5_PM (HWI2C_REG_BASE_PM+0x27*2+1) 313 #define REG_HWI2C_DMA_CMDDAT6_PM (HWI2C_REG_BASE_PM+0x28*2) 314 #define REG_HWI2C_DMA_CMDDAT7_PM (HWI2C_REG_BASE_PM+0x28*2+1) 315 #define REG_HWI2C_DMA_CMDLEN_PM (HWI2C_REG_BASE_PM+0x29*2) 316 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) 317 #define REG_HWI2C_DMA_DATLEN_PM (HWI2C_REG_BASE_PM+0x2A*2) // 4 bytes 318 #define REG_HWI2C_DMA_TXFRCNT_PM (HWI2C_REG_BASE_PM+0x2C*2) // 4 bytes 319 #define REG_HWI2C_DMA_SLVADR_PM (HWI2C_REG_BASE_PM+0x2E*2) 320 #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits 321 #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits 322 #define REG_HWI2C_DMA_SLVCFG_PM (HWI2C_REG_BASE_PM+0x2E*2+1) 323 #define _DMA_10BIT_MODE (__BIT2) 324 #define REG_HWI2C_DMA_CTL_TRIG_PM (HWI2C_REG_BASE_PM+0x2F*2) 325 #define _DMA_CTL_TRIG (__BIT0) 326 #define REG_HWI2C_DMA_CTL_RETRIG_PM (HWI2C_REG_BASE_PM+0x2F*2+1) 327 #define _DMA_CTL_RETRIG (__BIT0) 328 329 330 #endif 331