Searched refs:CFG_26_27_PVR4_STR2MI_MID (Results 1 – 11 of 11) sorted by relevance
1471 …#define CFG_26_27_PVR4_STR2MI_MID 0xffffffff //[31:27] : … macro
1510 …#define CFG_26_27_PVR4_STR2MI_MID 0xffffffff //[31:27] : … macro
4970 … REG32_W(&(_RegCtrl2->CFG_26_27), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_26_27_PVR4_STR2MI_MID); in HAL_PVR_SetBuf()5071 REG32_W(&(_RegCtrl2->CFG_26_27), (u32MidAddr0>>4) & CFG_26_27_PVR4_STR2MI_MID); in HAL_PVR_SetStr2Miu_MidAddr()
1512 …#define CFG_26_27_PVR4_STR2MI_MID 0xffffffff //[31:27] : … macro
1568 …#define CFG_26_27_PVR4_STR2MI_MID 0xffffffff //[31:27] : … macro
1530 …#define CFG_26_27_PVR4_STR2MI_MID 0xffffffff //[31:27] : … macro
1590 …#define CFG_26_27_PVR4_STR2MI_MID 0xffffffff //[31:27] : … macro
5480 … REG32_W(&(_RegCtrl2->CFG_26_27), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_26_27_PVR4_STR2MI_MID); in HAL_PVR_SetBuf()5582 REG32_W(&(_RegCtrl2->CFG_26_27), (u32MidAddr0>>4) & CFG_26_27_PVR4_STR2MI_MID); in HAL_PVR_SetStr2Miu_MidAddr()
5143 … REG32_W(&(_RegCtrl2->CFG_26_27), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_26_27_PVR4_STR2MI_MID); in HAL_PVR_SetBuf()5224 REG32_W(&(_RegCtrl2->CFG_26_27), (u32MidAddr0>>4) & CFG_26_27_PVR4_STR2MI_MID); in HAL_PVR_SetStr2Miu_MidAddr()