Home
last modified time | relevance | path

Searched refs:CFG_1F_20_PVR3_STR2MI_MID2 (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DregTSP.h1446 …#define CFG_1F_20_PVR3_STR2MI_MID2 0xffffffff //[31:27] : … macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h1485 …#define CFG_1F_20_PVR3_STR2MI_MID2 0xffffffff //[31:27] : … macro
H A DhalTSP.c4959 … REG32_W(&(_RegCtrl2->CFG_1F_20), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1F_20_PVR3_STR2MI_MID2); in HAL_PVR_SetBuf()
5067 REG32_W(&(_RegCtrl2->CFG_1F_20), (u32MidAddr1>>4) & CFG_1F_20_PVR3_STR2MI_MID2); in HAL_PVR_SetStr2Miu_MidAddr()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h1487 …#define CFG_1F_20_PVR3_STR2MI_MID2 0xffffffff //[31:27] : … macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h1543 …#define CFG_1F_20_PVR3_STR2MI_MID2 0xffffffff //[31:27] : … macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h1505 …#define CFG_1F_20_PVR3_STR2MI_MID2 0xffffffff //[31:27] : … macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h1505 …#define CFG_1F_20_PVR3_STR2MI_MID2 0xffffffff //[31:27] : … macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h1565 …#define CFG_1F_20_PVR3_STR2MI_MID2 0xffffffff //[31:27] : … macro
H A DhalTSP.c5469 … REG32_W(&(_RegCtrl2->CFG_1F_20), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1F_20_PVR3_STR2MI_MID2); in HAL_PVR_SetBuf()
5578 REG32_W(&(_RegCtrl2->CFG_1F_20), (u32MidAddr1>>4) & CFG_1F_20_PVR3_STR2MI_MID2); in HAL_PVR_SetStr2Miu_MidAddr()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DregTSP.h1505 …#define CFG_1F_20_PVR3_STR2MI_MID2 0xffffffff //[31:27] : … macro
H A DhalTSP.c5132 … REG32_W(&(_RegCtrl2->CFG_1F_20), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1F_20_PVR3_STR2MI_MID2); in HAL_PVR_SetBuf()
5220 REG32_W(&(_RegCtrl2->CFG_1F_20), (u32MidAddr1>>4) & CFG_1F_20_PVR3_STR2MI_MID2); in HAL_PVR_SetStr2Miu_MidAddr()