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Searched refs:CFG8_05 (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c5516 printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05)); in HAL_TSP_PVR_SPSConfig()
5517 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode in HAL_TSP_PVR_SPSConfig()
5523 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV in HAL_TSP_PVR_SPSConfig()
H A DregTSP.h2268 …REG16 CFG8_05; //SPS CTR mode control… member
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h2332 …REG16 CFG8_05; //SPS CTR mode control… member
H A DhalTSP.c6989 printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05)); in HAL_TSP_PVR_SPSConfig()
6990 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode in HAL_TSP_PVR_SPSConfig()
6996 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV in HAL_TSP_PVR_SPSConfig()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h2295 …REG16 CFG8_05; //SPS CTR mode control… member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h2421 …REG16 CFG8_05; //SPS CTR mode control… member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h2542 …REG16 CFG8_05; //SPS CTR mode control… member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h2542 …REG16 CFG8_05; //SPS CTR mode control… member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h2515 …REG16 CFG8_05; //SPS CTR mode control… member
H A DhalTSP.c7536 printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05)); in HAL_TSP_PVR_SPSConfig()
7537 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode in HAL_TSP_PVR_SPSConfig()
7543 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV in HAL_TSP_PVR_SPSConfig()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c7187 printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05)); in HAL_TSP_PVR_SPSConfig()
7188 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode in HAL_TSP_PVR_SPSConfig()
7194 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV in HAL_TSP_PVR_SPSConfig()
H A DregTSP.h2580 …REG16 CFG8_05; //SPS CTR mode control… member