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Searched refs:CFG6_2B (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DhalTSP.c398 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_ECO_TS_SYNC_OUT_DELAY); in HAL_TSP_HwPatch()
399 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_ECO_TS_SYNC_OUT_REVERSE_BLOCK); in HAL_TSP_HwPatch()
402 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_FIX_FILTER_NULL_PKT); in HAL_TSP_HwPatch()
416 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_OR_WRITE_FIX_FOR_NEW_MIU_ARBITER_DISABLE); in HAL_TSP_HwPatch()
3199 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1); in HAL_TSP_Filein_WbFsmRst()
3202 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2); in HAL_TSP_Filein_WbFsmRst()
3205 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF3); in HAL_TSP_Filein_WbFsmRst()
3220 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1); in HAL_TSP_Filein_WbFsmRst()
3223 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2); in HAL_TSP_Filein_WbFsmRst()
3226 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF3); in HAL_TSP_Filein_WbFsmRst()
H A DregTSP.h2406 REG16 CFG6_2B; member
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c321 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_ECO_TS_SYNC_OUT_DELAY); in HAL_TSP_HwPatch()
322 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_ECO_TS_SYNC_OUT_REVERSE_BLOCK); in HAL_TSP_HwPatch()
325 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_FIX_FILTER_NULL_PKT); in HAL_TSP_HwPatch()
3051 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1); in HAL_TSP_Filein_WbFsmRst()
3054 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2); in HAL_TSP_Filein_WbFsmRst()
3057 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF3); in HAL_TSP_Filein_WbFsmRst()
3072 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1); in HAL_TSP_Filein_WbFsmRst()
3075 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2); in HAL_TSP_Filein_WbFsmRst()
3078 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF3); in HAL_TSP_Filein_WbFsmRst()
H A DregTSP.h2329 REG16 CFG6_2B; member
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DhalTSP.c391 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_FIX_FILTER_NULL_PKT); in HAL_TSP_HwPatch()
2985 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1); in HAL_TSP_Filein_WbFsmRst()
2988 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2); in HAL_TSP_Filein_WbFsmRst()
2991 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF3); in HAL_TSP_Filein_WbFsmRst()
3006 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1); in HAL_TSP_Filein_WbFsmRst()
3009 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2); in HAL_TSP_Filein_WbFsmRst()
3012 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF3); in HAL_TSP_Filein_WbFsmRst()
H A DregTSP.h2229 REG16 CFG6_2B; member
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c307 …REG16_SET(&_RegCtrl6->CFG6_2B, TSP_ECO_FIQ_INPUT | TSP_ECO_TS_SYNC_OUT_DELAY | TSP_ECO_TS_SYNC_OUT… in HAL_TSP_HwPatch()
2107 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1); in HAL_TSP_Filein_WbFsmRst()
2110 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2); in HAL_TSP_Filein_WbFsmRst()
2125 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1); in HAL_TSP_Filein_WbFsmRst()
2128 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2); in HAL_TSP_Filein_WbFsmRst()
H A DregTSP.h2197 REG16 CFG6_2B; member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h2231 REG16 CFG6_2B; member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h2351 REG16 CFG6_2B; member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h2329 REG16 CFG6_2B; member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h2329 REG16 CFG6_2B; member