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Searched refs:CFG5_7D_DIS_PKT_CNT_V3D_CLR (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c5135 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_DisPKTCnt_Clear()
5136 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_DisPKTCnt_Clear()
6307 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
6308 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
H A DregTSP.h2087 #define CFG5_7D_DIS_PKT_CNT_V3D_CLR 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c6672 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_DisPKTCnt_Clear()
6673 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_DisPKTCnt_Clear()
8063 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
8064 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
H A DregTSP.h2221 #define CFG5_7D_DIS_PKT_CNT_V3D_CLR 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DhalTSP.c7044 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_DisPKTCnt_Clear()
7045 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_DisPKTCnt_Clear()
8480 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
8481 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_Debug_DisPktCnt_Clear()
H A DregTSP.h2295 #define CFG5_7D_DIS_PKT_CNT_V3D_CLR 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h2125 #define CFG5_7D_DIS_PKT_CNT_V3D_CLR 0x0200 macro
H A DhalTSP.c6498 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_DisPKTCnt_Clear()
6499 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR); in HAL_TSP_DisPKTCnt_Clear()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h2127 #define CFG5_7D_DIS_PKT_CNT_V3D_CLR 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h2242 #define CFG5_7D_DIS_PKT_CNT_V3D_CLR 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h2221 #define CFG5_7D_DIS_PKT_CNT_V3D_CLR 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h2221 #define CFG5_7D_DIS_PKT_CNT_V3D_CLR 0x0200 macro