Home
last modified time | relevance | path

Searched refs:reg_cfg (Results 1 – 9 of 9) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu580_common.c15 MppDevRegOffCfgs *reg_cfg = cfg->reg_cfg; in vepu580_set_osd() local
77 if (reg_cfg) in vepu580_set_osd()
78 … mpp_dev_multi_offset_update(reg_cfg, VEPU580_OSD_ADDR_IDX_BASE + k, tmp->buf_offset); in vepu580_set_osd()
H A Dvepu5xx_common.h72 MppDevRegOffCfgs *reg_cfg; member
/rockchip-linux_mpp/mpp/hal/vpu/jpege/
H A Dhal_jpege_vepu2_v2.c48 MppDevRegOffCfgs *reg_cfg; member
129 if (ctx_ext->reg_cfg) { in hal_jpege_vepu2_deinit()
130 mpp_dev_multi_offset_deinit(ctx_ext->reg_cfg); in hal_jpege_vepu2_deinit()
131 ctx_ext->reg_cfg = NULL; in hal_jpege_vepu2_deinit()
318 if (!ctx_ext->reg_cfg) in hal_jpege_vepu2_get_task()
319 mpp_dev_multi_offset_init(&ctx_ext->reg_cfg, 24); in hal_jpege_vepu2_get_task()
584 MppDevRegOffCfgs *reg_cfg = ctx_ext->reg_cfg; in multi_core_start() local
620 mpp_dev_multi_offset_reset(reg_cfg); in multi_core_start()
685 mpp_dev_multi_offset_update(reg_cfg, VEPU2_REG_INPUT_Y, cfg.offset_byte[0]); in multi_core_start()
686 mpp_dev_multi_offset_update(reg_cfg, VEPU2_REG_INPUT_U, cfg.offset_byte[1]); in multi_core_start()
[all …]
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu510.c96 MppDevRegOffCfgs *reg_cfg; member
137 MppDevRegOffCfgs *reg_cfg; member
1058 if (frm->reg_cfg) { in hal_h265e_v510_deinit()
1059 mpp_dev_multi_offset_deinit(frm->reg_cfg); in hal_h265e_v510_deinit()
1060 frm->reg_cfg = NULL; in hal_h265e_v510_deinit()
1085 if (ctx->reg_cfg) { in hal_h265e_v510_deinit()
1086 mpp_dev_multi_offset_deinit(ctx->reg_cfg); in hal_h265e_v510_deinit()
1087 ctx->reg_cfg = NULL; in hal_h265e_v510_deinit()
1141 mpp_dev_multi_offset_init(&ctx->reg_cfg, 24); in hal_h265e_v510_init()
1642 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, ctx->fbc_header_len); in vepu510_h265_set_hw_address()
[all …]
H A Dhal_h265e_vepu580.c155 MppDevRegOffCfgs *reg_cfg; member
1441 if (frm->reg_cfg) { in hal_h265e_v580_deinit()
1442 mpp_dev_multi_offset_deinit(frm->reg_cfg); in hal_h265e_v580_deinit()
1443 frm->reg_cfg = NULL; in hal_h265e_v580_deinit()
1549 mpp_dev_multi_offset_init(&frm_cfg->reg_cfg, 24); in hal_h265e_v580_init()
1550 frm_cfg->osd_cfg.reg_cfg = frm_cfg->reg_cfg; in hal_h265e_v580_init()
2466 mpp_dev_multi_offset_update(frm->reg_cfg, 164, ctx->fbc_header_len); in vepu580_h265_set_hw_address()
2475 mpp_dev_multi_offset_update(frm->reg_cfg, 166, ctx->fbc_header_len); in vepu580_h265_set_hw_address()
2529 mpp_dev_multi_offset_update(frm->reg_cfg, 175, mpp_packet_get_length(task->packet)); in vepu580_h265_set_hw_address()
2530 mpp_dev_multi_offset_update(frm->reg_cfg, 172, mpp_buffer_get_size(enc_task->output)); in vepu580_h265_set_hw_address()
[all …]
H A Dhal_h265e_vepu511.c95 MppDevRegOffCfgs *reg_cfg; member
138 MppDevRegOffCfgs *reg_cfg; member
453 if (frm->reg_cfg) { in hal_h265e_vepu511_deinit()
454 mpp_dev_multi_offset_deinit(frm->reg_cfg); in hal_h265e_vepu511_deinit()
455 frm->reg_cfg = NULL; in hal_h265e_vepu511_deinit()
480 if (ctx->reg_cfg) { in hal_h265e_vepu511_deinit()
481 mpp_dev_multi_offset_deinit(ctx->reg_cfg); in hal_h265e_vepu511_deinit()
482 ctx->reg_cfg = NULL; in hal_h265e_vepu511_deinit()
536 mpp_dev_multi_offset_init(&ctx->reg_cfg, 24); in hal_h265e_vepu511_init()
685 mpp_dev_multi_offset_update(ctx->reg_cfg, 164, width_align * height_align); in vepu511_h265e_save_pass1_patch()
[all …]
H A Dhal_h265e_vepu541.c631 ctx->osd_cfg.reg_cfg = NULL; in hal_h265e_v541_init()
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu580.c372 p->osd_cfg.reg_cfg = NULL; in hal_h264e_vepu580_init()
399 p->osd_cfg.reg_cfg = p->offsets; in hal_h264e_vepu580_init()
H A Dhal_h264e_vepu541.c195 p->osd_cfg.reg_cfg = NULL; in hal_h264e_vepu541_init()