96     MppDevRegOffCfgs    *reg_cfg;  member
137     MppDevRegOffCfgs    *reg_cfg;  member
1058         if (frm->reg_cfg) {  in hal_h265e_v510_deinit()
1059             mpp_dev_multi_offset_deinit(frm->reg_cfg);  in hal_h265e_v510_deinit()
1060             frm->reg_cfg = NULL;  in hal_h265e_v510_deinit()
1085     if (ctx->reg_cfg) {  in hal_h265e_v510_deinit()
1086         mpp_dev_multi_offset_deinit(ctx->reg_cfg);  in hal_h265e_v510_deinit()
1087         ctx->reg_cfg = NULL;  in hal_h265e_v510_deinit()
1141     mpp_dev_multi_offset_init(&ctx->reg_cfg, 24);  in hal_h265e_v510_init()
1642         mpp_dev_multi_offset_update(ctx->reg_cfg, 164, ctx->fbc_header_len);  in vepu510_h265_set_hw_address()
1651     mpp_dev_multi_offset_update(ctx->reg_cfg, 166, ctx->fbc_header_len);  in vepu510_h265_set_hw_address()
1672     mpp_dev_multi_offset_update(ctx->reg_cfg, 174, mpp_packet_get_length(task->packet));  in vepu510_h265_set_hw_address()
1673     mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(enc_task->output));  in vepu510_h265_set_hw_address()
1708     mpp_dev_multi_offset_update(ctx->reg_cfg, 164, 0);  in vepu510_h265e_save_pass1_patch()
1745     ret = mpp_dev_multi_offset_update(ctx->reg_cfg, 161, 2 * hor_stride);  in vepu510_h265e_use_pass1_patch()
1765         mpp_dev_multi_offset_update(ctx->reg_cfg, 178, ctx->ext_line_buf_size);  in setup_vepu510_ext_line_buf()
2049     ret = vepu510_h265_set_patch_info(syn, (VepuFmt)fmt->format, ctx->reg_cfg, enc_task);  in hal_h265e_v510_gen_regs()
2187     ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, ctx->reg_cfg);  in hal_h265e_v510_start()