95     MppDevRegOffCfgs    *reg_cfg;  member
138     MppDevRegOffCfgs    *reg_cfg;  member
453         if (frm->reg_cfg) {  in hal_h265e_vepu511_deinit()
454             mpp_dev_multi_offset_deinit(frm->reg_cfg);  in hal_h265e_vepu511_deinit()
455             frm->reg_cfg = NULL;  in hal_h265e_vepu511_deinit()
480     if (ctx->reg_cfg) {  in hal_h265e_vepu511_deinit()
481         mpp_dev_multi_offset_deinit(ctx->reg_cfg);  in hal_h265e_vepu511_deinit()
482         ctx->reg_cfg = NULL;  in hal_h265e_vepu511_deinit()
536     mpp_dev_multi_offset_init(&ctx->reg_cfg, 24);  in hal_h265e_vepu511_init()
685     mpp_dev_multi_offset_update(ctx->reg_cfg, 164, width_align * height_align);  in vepu511_h265e_save_pass1_patch()
723     ret = mpp_dev_multi_offset_update(ctx->reg_cfg, 161, width_align * height_align);  in vepu511_h265e_use_pass1_patch()
740         mpp_dev_multi_offset_update(ctx->reg_cfg, 178, ctx->ext_line_buf_size);  in setup_vepu511_ext_line_buf()
1104         mpp_dev_multi_offset_update(ctx->reg_cfg, 164, ctx->fbc_header_len);  in vepu511_h265_set_hw_address()
1113     mpp_dev_multi_offset_update(ctx->reg_cfg, 166, ctx->fbc_header_len);  in vepu511_h265_set_hw_address()
1135     mpp_dev_multi_offset_update(ctx->reg_cfg, 174, mpp_packet_get_length(task->packet));  in vepu511_h265_set_hw_address()
1136     mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(enc_task->output));  in vepu511_h265_set_hw_address()
2203     ret = vepu511_h265_set_patch_info(syn, (VepuFmt)fmt->format, ctx->reg_cfg, enc_task);  in hal_h265e_vepu511_gen_regs()
2379     ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, ctx->reg_cfg);  in hal_h265e_vepu511_start()