Searched refs:pic_width (Results 1 – 9 of 9) sorted by relevance
981 mb_wd64 = (syn->pp.pic_width + 63) / 64; in vepu541_h265_set_rc_regs()1236 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6; in vepu541_h265_set_me_regs()1245 if (syn->pp.pic_width < merangx + 60 || syn->pp.pic_width <= 352) { in vepu541_h265_set_me_regs()1246 if (merangx > syn->pp.pic_width ) { in vepu541_h265_set_me_regs()1247 merangx = syn->pp.pic_width; in vepu541_h265_set_me_regs()1295 if (syn->pp.pic_width > 2688) { in vepu541_h265_set_me_regs()1297 } else if (syn->pp.pic_width > 2048) { in vepu541_h265_set_me_regs()1335 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6; in vepu540_h265_set_me_ram()1513 pic_width_align8 = (syn->pp.pic_width + 7) & (~7); in hal_h265e_v541_gen_regs()1515 pic_wd64 = (syn->pp.pic_width + 63) / 64; in hal_h265e_v541_gen_regs()[all …]
1901 mb_wd64 = (syn->pp.pic_width + 63) / 64; in vepu580_h265_set_rc_regs()2320 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6; in vepu580_h265_set_me_regs()2329 if (syn->pp.pic_width < merangx + 60 || syn->pp.pic_width <= 352) { in vepu580_h265_set_me_regs()2330 if (merangx > syn->pp.pic_width ) { in vepu580_h265_set_me_regs()2331 merangx = syn->pp.pic_width; in vepu580_h265_set_me_regs()2384 if (syn->pp.pic_width > 2688) { in vepu580_h265_set_me_regs()2386 } else if (syn->pp.pic_width > 2048) { in vepu580_h265_set_me_regs()2691 pic_width_align8 = (syn->pp.pic_width + 7) & (~7); in hal_h265e_v580_gen_regs()2693 pic_wd64 = (syn->pp.pic_width + 63) / 64; in hal_h265e_v580_gen_regs()2743 reg_base->reg0197_src_fill.pic_wfill = (syn->pp.pic_width & 0x7) in hal_h265e_v580_gen_regs()[all …]
716 RK_S32 mb_wd32 = (syn->pp.pic_width + 31) / 32; in vepu540c_h265_set_rc_regs()1206 pic_width_align8 = (syn->pp.pic_width + 7) & (~7); in hal_h265e_v540c_gen_regs()1208 pic_wd32 = (syn->pp.pic_width + 31) / 32; in hal_h265e_v540c_gen_regs()1262 reg_base->reg0197_src_fill.pic_wfill = (syn->pp.pic_width & 0x7) in hal_h265e_v540c_gen_regs()1263 ? (8 - (syn->pp.pic_width & 0x7)) : 0; in hal_h265e_v540c_gen_regs()
1307 RK_S32 mb_wd32 = (syn->pp.pic_width + 31) / 32; in vepu510_h265_set_rc_regs()1950 pic_width_align8 = (syn->pp.pic_width + 7) & (~7); in hal_h265e_v510_gen_regs()1952 pic_wd32 = (syn->pp.pic_width + 31) / 32; in hal_h265e_v510_gen_regs()1997 reg_frm->common.src_fill.pic_wfill = (syn->pp.pic_width & 0x7) in hal_h265e_v510_gen_regs()1998 ? (8 - (syn->pp.pic_width & 0x7)) : 0; in hal_h265e_v510_gen_regs()
869 pic_width_align8 = (syn->pp.pic_width + 7) & (~7); in vepu511_h265_set_prep()871 pic_wd32 = (syn->pp.pic_width + 31) / 32; in vepu511_h265_set_prep()876 reg_frm->common.src_fill.pic_wfill = (syn->pp.pic_width & 0x7) in vepu511_h265_set_prep()877 ? (8 - (syn->pp.pic_width & 0x7)) : 0; in vepu511_h265_set_prep()1267 RK_S32 mb_wd32 = (syn->pp.pic_width + 31) / 32; in vepu511_h265_set_rc_regs()
28 RK_U16 pic_width; member
158 RK_U32 pic_width, pic_height; in prepare_spspps() local161 pic_width = 16 * (pp->wFrameWidthInMbsMinus1 + 1); in prepare_spspps()177 mpp_put_bits(&bp, pic_width, 16); in prepare_spspps()
171 RK_U32 pic_width, pic_height; in prepare_spspps() local174 pic_width = 16 * (pp->wFrameWidthInMbsMinus1 + 1); in prepare_spspps()190 mpp_put_bits(&bp, pic_width, 16); in prepare_spspps()
48 pp->pic_width = h->cfg->prep.width; in fill_picture_parameters()