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Searched refs:hw (Results 1 – 19 of 19) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu510_tune.c90 MppEncHwCfg *hw = &ctx->cfg->hw; in vepu510_h265e_tune_aq_prepare() local
93 memcpy(hw->aq_thrd_i, aq_thd_smt_I, sizeof(hw->aq_thrd_i)); in vepu510_h265e_tune_aq_prepare()
94 memcpy(hw->aq_thrd_p, aq_thd_smt_P, sizeof(hw->aq_thrd_p)); in vepu510_h265e_tune_aq_prepare()
95 memcpy(hw->aq_step_i, aq_qp_delta_smt_I, sizeof(hw->aq_step_i)); in vepu510_h265e_tune_aq_prepare()
96 memcpy(hw->aq_step_p, aq_qp_delta_smt_P, sizeof(hw->aq_step_p)); in vepu510_h265e_tune_aq_prepare()
98 memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i)); in vepu510_h265e_tune_aq_prepare()
99 memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p)); in vepu510_h265e_tune_aq_prepare()
100 memcpy(hw->aq_step_i, aq_qp_delta_default, sizeof(hw->aq_step_i)); in vepu510_h265e_tune_aq_prepare()
101 memcpy(hw->aq_step_p, aq_qp_delta_default, sizeof(hw->aq_step_p)); in vepu510_h265e_tune_aq_prepare()
111 MppEncHwCfg *hw = &ctx->cfg->hw; in vepu510_h265e_tune_aq() local
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H A Dhal_h265e_vepu511.c541 MppEncHwCfg *hw = &cfg->cfg->hw; in hal_h265e_vepu511_init() local
544 hw->qp_delta_row_i = 2; in hal_h265e_vepu511_init()
545 hw->qp_delta_row = 2; in hal_h265e_vepu511_init()
546 hw->qbias_i = 171; in hal_h265e_vepu511_init()
547 hw->qbias_p = 85; in hal_h265e_vepu511_init()
548 hw->qbias_en = 0; in hal_h265e_vepu511_init()
550 for (j = 0; j < MPP_ARRAY_ELEMS(hw->mode_bias); j++) in hal_h265e_vepu511_init()
551 hw->mode_bias[j] = 8; in hal_h265e_vepu511_init()
1224 MppEncHwCfg *hw = &cfg->hw; in vepu511_h265_set_vsp_filtering() local
1229 (hw->flt_str_i == 0) && (hw->flt_str_p == 0)) { in vepu511_h265_set_vsp_filtering()
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H A Dhal_h265e_vepu580.c692 static void vepu580_h265_rdo_bias_cfg (vepu580_rdo_cfg *reg, MppEncHwCfg *hw) in vepu580_h265_rdo_bias_cfg() argument
696 RK_U8 bias = h265e_mode_bias[hw->mode_bias[4]]; in vepu580_h265_rdo_bias_cfg()
712 if (hw->skip_bias_en) { in vepu580_h265_rdo_bias_cfg()
713 bias = h265e_mode_bias[hw->skip_bias]; in vepu580_h265_rdo_bias_cfg()
716 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = hw->skip_sad < 24 ? hw->skip_sad : 24; in vepu580_h265_rdo_bias_cfg()
717 p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = hw->skip_sad < 4 ? hw->skip_sad : 4; in vepu580_h265_rdo_bias_cfg()
718 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = hw->skip_sad < 6 ? hw->skip_sad : 6; in vepu580_h265_rdo_bias_cfg()
719 p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = hw->skip_sad; in vepu580_h265_rdo_bias_cfg()
739 bias = h265e_mode_bias[hw->mode_bias[0]]; in vepu580_h265_rdo_bias_cfg()
755 bias = h265e_mode_bias[hw->mode_bias[5]]; in vepu580_h265_rdo_bias_cfg()
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H A Dhal_h265e_vepu540c.c425 MppEncHwCfg *hw = &ctx->cfg->hw; in vepu540c_h265_global_cfg_set() local
434 rc_regs->aq_tthd[i] = hw->aq_thrd_i[i]; in vepu540c_h265_global_cfg_set()
435 rc_regs->aq_step[i] = hw->aq_step_i[i] & 0x3f; in vepu540c_h265_global_cfg_set()
441 rc_regs->aq_tthd[i] = hw->aq_thrd_p[i]; in vepu540c_h265_global_cfg_set()
442 rc_regs->aq_step[i] = hw->aq_step_p[i] & 0x3f; in vepu540c_h265_global_cfg_set()
449 if (hw->qbias_en) { in vepu540c_h265_global_cfg_set()
450 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = hw->qbias_i; in vepu540c_h265_global_cfg_set()
451 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = hw->qbias_p; in vepu540c_h265_global_cfg_set()
535 MppEncHwCfg *hw = &cfg->cfg->hw; in hal_h265e_v540c_init() local
537 hw->qp_delta_row_i = 2; in hal_h265e_v540c_init()
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H A Dhal_h265e_vepu541.c512 MppEncHwCfg *hw = &ctx->cfg->hw; in vepu541_h265_set_l2_regs() local
571 regs->aq_tthd[i] = hw->aq_thrd_i[i]; in vepu541_h265_set_l2_regs()
572 regs->aq_step[i] = hw->aq_step_i[i] & 0x3f; in vepu541_h265_set_l2_regs()
576 regs->aq_tthd[i] = hw->aq_thrd_p[i]; in vepu541_h265_set_l2_regs()
577 regs->aq_step[i] = hw->aq_step_p[i] & 0x3f; in vepu541_h265_set_l2_regs()
581 if (hw->qbias_en) { in vepu541_h265_set_l2_regs()
582 regs->rdo_quant.quant_f_bias_I = hw->qbias_i; in vepu541_h265_set_l2_regs()
583 regs->rdo_quant.quant_f_bias_P = hw->qbias_p; in vepu541_h265_set_l2_regs()
639 MppEncHwCfg *hw = &cfg->cfg->hw; in hal_h265e_v541_init() local
641 hw->qp_delta_row_i = 0; in hal_h265e_v541_init()
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H A Dhal_h265e_vepu580_tune.c389 MppEncHwCfg *hw = &ctx->cfg->hw; in vepu580_h265e_tune_reg_patch() local
404 if (!hw->skip_bias_en) in vepu580_h265e_tune_reg_patch()
474 if (hw->qbias_en) { in vepu580_h265e_tune_reg_patch()
475 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = hw->qbias_i ? hw->qbias_i : 171; in vepu580_h265e_tune_reg_patch()
476 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = hw->qbias_p ? hw->qbias_p : 85; in vepu580_h265e_tune_reg_patch()
H A Dhal_h265e_vepu510.c935 MppEncHwCfg *hw = &ctx->cfg->hw; in vepu510_h265_global_cfg_set() local
961 if (hw->qbias_en) { in vepu510_h265_global_cfg_set()
962 reg_param->qnt_bias_comb.qnt_f_bias_i = hw->qbias_i; in vepu510_h265_global_cfg_set()
963 reg_param->qnt_bias_comb.qnt_f_bias_p = hw->qbias_p; in vepu510_h265_global_cfg_set()
1146 MppEncHwCfg *hw = &cfg->cfg->hw; in hal_h265e_v510_init() local
1149 hw->qp_delta_row_i = 2; in hal_h265e_v510_init()
1150 hw->qp_delta_row = 2; in hal_h265e_v510_init()
1151 hw->qbias_i = 171; in hal_h265e_v510_init()
1152 hw->qbias_p = 85; in hal_h265e_v510_init()
1153 hw->qbias_en = 0; in hal_h265e_v510_init()
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/rockchip-linux_mpp/mpp/base/
H A Dmpp_enc_cfg.c218 STRUCT_START(hw); \
219 …ENTRY(prefix, s32, rk_s32, qp_row, FLAG_BASE(0), hw, qp…
220 …ENTRY(prefix, s32, rk_s32, qp_row_i, FLAG_INCR, hw, qp…
221 …STRCT(prefix, st, void *, aq_thrd_i, FLAG_INCR, hw, aq…
222 …STRCT(prefix, st, void *, aq_thrd_p, FLAG_INCR, hw, aq…
223 …STRCT(prefix, st, void *, aq_step_i, FLAG_INCR, hw, aq…
224 …STRCT(prefix, st, void *, aq_step_p, FLAG_INCR, hw, aq…
225 …ENTRY(prefix, s32, rk_s32, mb_rc_disable, FLAG_INCR, hw, mb…
226 …STRCT(prefix, st, void *, aq_rnge_arr, FLAG_INCR, hw, aq…
227 …STRCT(prefix, st, void *, mode_bias, FLAG_INCR, hw, mo…
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/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu580.c378 MppEncHwCfg *hw = &cfg->cfg->hw; in hal_h264e_vepu580_init() local
380 hw->qp_delta_row_i = 2; in hal_h264e_vepu580_init()
381 hw->qp_delta_row = 2; in hal_h264e_vepu580_init()
382 hw->extra_buf = 1; in hal_h264e_vepu580_init()
383 hw->qbias_i = 683; in hal_h264e_vepu580_init()
384 hw->qbias_p = 341; in hal_h264e_vepu580_init()
385 hw->qbias_en = 0; in hal_h264e_vepu580_init()
387 memcpy(hw->aq_thrd_i, h264_aq_tthd_default, sizeof(hw->aq_thrd_i)); in hal_h264e_vepu580_init()
388 memcpy(hw->aq_thrd_p, h264_aq_tthd_default, sizeof(hw->aq_thrd_p)); in hal_h264e_vepu580_init()
389 memcpy(hw->aq_step_i, h264_I_aq_step_default, sizeof(hw->aq_step_i)); in hal_h264e_vepu580_init()
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H A Dhal_h264e_vepu541.c201 MppEncHwCfg *hw = &cfg->cfg->hw; in hal_h264e_vepu541_init() local
203 hw->qp_delta_row_i = 0; in hal_h264e_vepu541_init()
204 hw->qp_delta_row = 2; in hal_h264e_vepu541_init()
205 hw->qbias_i = 683; in hal_h264e_vepu541_init()
206 hw->qbias_p = 341; in hal_h264e_vepu541_init()
207 hw->qbias_en = 0; in hal_h264e_vepu541_init()
209 memcpy(hw->aq_thrd_i, h264_aq_tthd_default, sizeof(hw->aq_thrd_i)); in hal_h264e_vepu541_init()
210 memcpy(hw->aq_thrd_p, h264_aq_tthd_default, sizeof(hw->aq_thrd_p)); in hal_h264e_vepu541_init()
211 memcpy(hw->aq_step_i, h264_I_aq_step_default, sizeof(hw->aq_step_i)); in hal_h264e_vepu541_init()
212 memcpy(hw->aq_step_p, h264_P_aq_step_default, sizeof(hw->aq_step_p)); in hal_h264e_vepu541_init()
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H A Dhal_h264e_vepu540c.c169 MppEncHwCfg *hw = &cfg->cfg->hw; in hal_h264e_vepu540c_init() local
171 hw->qp_delta_row_i = 1; in hal_h264e_vepu540c_init()
172 hw->qp_delta_row = 2; in hal_h264e_vepu540c_init()
173 hw->qbias_i = 683; in hal_h264e_vepu540c_init()
174 hw->qbias_p = 341; in hal_h264e_vepu540c_init()
175 hw->qbias_en = 0; in hal_h264e_vepu540c_init()
177 memcpy(hw->aq_thrd_i, h264_aq_tthd_default, sizeof(hw->aq_thrd_i)); in hal_h264e_vepu540c_init()
178 memcpy(hw->aq_thrd_p, h264_aq_tthd_default, sizeof(hw->aq_thrd_p)); in hal_h264e_vepu540c_init()
179 memcpy(hw->aq_step_i, h264_I_aq_step_default, sizeof(hw->aq_step_i)); in hal_h264e_vepu540c_init()
180 memcpy(hw->aq_step_p, h264_P_aq_step_default, sizeof(hw->aq_step_p)); in hal_h264e_vepu540c_init()
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H A Dhal_h264e_vepu510.c356 MppEncHwCfg *hw = &cfg->cfg->hw; in hal_h264e_vepu510_init() local
358 hw->qp_delta_row_i = 1; in hal_h264e_vepu510_init()
359 hw->qp_delta_row = 2; in hal_h264e_vepu510_init()
360 hw->extra_buf = 1; in hal_h264e_vepu510_init()
361 hw->qbias_i = 683; in hal_h264e_vepu510_init()
362 hw->qbias_p = 341; in hal_h264e_vepu510_init()
363 hw->qbias_en = 0; in hal_h264e_vepu510_init()
365 memcpy(hw->aq_thrd_i, h264_aq_tthd_default, sizeof(hw->aq_thrd_i)); in hal_h264e_vepu510_init()
366 memcpy(hw->aq_thrd_p, h264_aq_tthd_default, sizeof(hw->aq_thrd_p)); in hal_h264e_vepu510_init()
367 memcpy(hw->aq_step_i, h264_I_aq_step_default, sizeof(hw->aq_step_i)); in hal_h264e_vepu510_init()
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H A Dhal_h264e_vepu580_tune.c127 MppEncHwCfg *hw = &ctx->cfg->hw; in vepu580_h264e_tune_reg_patch() local
219 if (hw->qbias_en) { in vepu580_h264e_tune_reg_patch()
220 regs->reg_s3.RDO_QUANT.quant_f_bias_I = hw->qbias_i ? hw->qbias_i : 683; in vepu580_h264e_tune_reg_patch()
221 regs->reg_s3.RDO_QUANT.quant_f_bias_P = hw->qbias_p ? hw->qbias_p : 341; in vepu580_h264e_tune_reg_patch()
H A Dhal_h264e_vepu511.c355 MppEncHwCfg *hw = &cfg->cfg->hw; in hal_h264e_vepu511_init() local
357 hw->qp_delta_row_i = 1; in hal_h264e_vepu511_init()
358 hw->qp_delta_row = 2; in hal_h264e_vepu511_init()
359 hw->extra_buf = 1; in hal_h264e_vepu511_init()
360 hw->qbias_i = 683; in hal_h264e_vepu511_init()
361 hw->qbias_p = 341; in hal_h264e_vepu511_init()
362 hw->qbias_en = 0; in hal_h264e_vepu511_init()
364 memcpy(hw->aq_thrd_i, h264_aq_tthd_default, sizeof(hw->aq_thrd_i)); in hal_h264e_vepu511_init()
365 memcpy(hw->aq_thrd_p, h264_aq_tthd_default, sizeof(hw->aq_thrd_p)); in hal_h264e_vepu511_init()
366 memcpy(hw->aq_step_i, h264_I_aq_step_default, sizeof(hw->aq_step_i)); in hal_h264e_vepu511_init()
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/rockchip-linux_mpp/mpp/inc/
H A Dmpp_enc_cfg.h34 MppEncHwCfg hw; member
/rockchip-linux_mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu_v2.c516 MppEncHwCfg* hw_cfg = &cfg->hw; in h264e_vepu_mbrc_setup()
/rockchip-linux_mpp/mpp/codec/enc/h264/
H A Dh264e_dpb.c143 if (cfg->hw.extra_buf) in h264e_dpb_setup()
/rockchip-linux_mpp/
H A DCHANGELOG.md293 - [hal_avsd]: enable hw dec timeout
616 - [h265e]: fix hw stream size check error
/rockchip-linux_mpp/mpp/codec/
H A Dmpp_enc_impl.c848 MppEncHwCfg *cfg = &enc->cfg->hw; in proc_hw_cfg()
849 MppEncHwCfg *set = &enc->set->hw; in proc_hw_cfg()