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Searched refs:cfg1 (Results 1 – 9 of 9) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/jpege/
H A Dhal_jpege_vepu540c.c243 MppDevRegRdCfg cfg1; in hal_jpege_v540c_start() local
282 cfg1.reg = &reg_out->hw_status; in hal_jpege_v540c_start()
283 cfg1.size = sizeof(RK_U32); in hal_jpege_v540c_start()
284 cfg1.offset = VEPU540C_REG_BASE_HW_STATUS; in hal_jpege_v540c_start()
286 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_jpege_v540c_start()
292 cfg1.reg = &reg_out->st; in hal_jpege_v540c_start()
293 cfg1.size = sizeof(JpegV540cStatus) - 4; in hal_jpege_v540c_start()
294 cfg1.offset = VEPU540C_STATUS_OFFSET; in hal_jpege_v540c_start()
296 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_jpege_v540c_start()
H A Dhal_jpege_vepu511.c472 MppDevRegRdCfg cfg1; in hal_jpege_vepu511_start() local
521 cfg1.reg = &reg_out->hw_status; in hal_jpege_vepu511_start()
522 cfg1.size = sizeof(RK_U32); in hal_jpege_vepu511_start()
523 cfg1.offset = VEPU511_REG_BASE_HW_STATUS; in hal_jpege_vepu511_start()
525 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_jpege_vepu511_start()
531 cfg1.reg = &reg_out->st; in hal_jpege_vepu511_start()
532 cfg1.size = sizeof(JpegV511Status) - 4; in hal_jpege_vepu511_start()
533 cfg1.offset = VEPU511_STATUS_OFFSET; in hal_jpege_vepu511_start()
535 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_jpege_vepu511_start()
/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu511_common.c57 reg->cfg1.osd_lt_xcrd = region->lt_x; in vepu511_set_osd()
58 reg->cfg1.osd_lt_ycrd = region->lt_y; in vepu511_set_osd()
62 reg->cfg1.osd_endn = region->osd_endn; in vepu511_set_osd()
H A Dvepu511_common.h1454 } cfg1; member
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu541.c1686 MppDevRegRdCfg cfg1; in hal_h265e_v540_start() local
1717 cfg1.reg = &reg_out->hw_status; in hal_h265e_v540_start()
1718 cfg1.size = sizeof(RK_U32); in hal_h265e_v540_start()
1719 cfg1.offset = VEPU541_REG_BASE_HW_STATUS; in hal_h265e_v540_start()
1721 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_h265e_v540_start()
1727 cfg1.reg = &reg_out->st_bsl; in hal_h265e_v540_start()
1728 cfg1.size = sizeof(H265eV541IoctlOutputElem) - 4; in hal_h265e_v540_start()
1729 cfg1.offset = VEPU541_REG_BASE_STATISTICS; in hal_h265e_v540_start()
1731 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_h265e_v540_start()
1808 MppDevRegRdCfg cfg1; in hal_h265e_v541_start() local
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H A Dhal_h265e_vepu540c.c1333 MppDevRegRdCfg cfg1; in hal_h265e_v540c_start() local
1424 cfg1.reg = &reg_out->hw_status; in hal_h265e_v540c_start()
1425 cfg1.size = sizeof(RK_U32); in hal_h265e_v540c_start()
1426 cfg1.offset = VEPU540C_REG_BASE_HW_STATUS; in hal_h265e_v540c_start()
1428 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_h265e_v540c_start()
1434 cfg1.reg = &reg_out->st; in hal_h265e_v540c_start()
1435 cfg1.size = sizeof(H265eV540cStatusElem) - 4; in hal_h265e_v540c_start()
1436 cfg1.offset = VEPU540C_STATUS_OFFSET; in hal_h265e_v540c_start()
1438 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_h265e_v540c_start()
H A Dhal_h265e_vepu510.c2086 MppDevRegRdCfg cfg1; in hal_h265e_v510_start() local
2193 cfg1.reg = &reg_out->hw_status; in hal_h265e_v510_start()
2194 cfg1.size = sizeof(RK_U32); in hal_h265e_v510_start()
2195 cfg1.offset = VEPU510_REG_BASE_HW_STATUS; in hal_h265e_v510_start()
2197 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_h265e_v510_start()
2203 cfg1.reg = &reg_out->st; in hal_h265e_v510_start()
2204 cfg1.size = sizeof(H265eV510StatusElem) - 4; in hal_h265e_v510_start()
2205 cfg1.offset = VEPU510_STATUS_OFFSET; in hal_h265e_v510_start()
2207 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_h265e_v510_start()
H A Dhal_h265e_vepu511.c2247 MppDevRegRdCfg cfg1; in hal_h265e_vepu511_start() local
2385 cfg1.reg = &reg_out->hw_status; in hal_h265e_vepu511_start()
2386 cfg1.size = sizeof(RK_U32); in hal_h265e_vepu511_start()
2387 cfg1.offset = VEPU511_REG_BASE_HW_STATUS; in hal_h265e_vepu511_start()
2389 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_h265e_vepu511_start()
2395 cfg1.reg = &reg_out->st; in hal_h265e_vepu511_start()
2396 cfg1.size = sizeof(H265eV511StatusElem) - 4; in hal_h265e_vepu511_start()
2397 cfg1.offset = VEPU511_STATUS_OFFSET; in hal_h265e_vepu511_start()
2399 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1); in hal_h265e_vepu511_start()
H A Dhal_h265e_vepu580.c2167 MppDevRegRdCfg cfg1; in hal_h265e_v580_send_regs() local
2264 cfg1.reg = &reg_out->hw_status; in hal_h265e_v580_send_regs()
2265 cfg1.size = sizeof(RK_U32); in hal_h265e_v580_send_regs()
2266 cfg1.offset = VEPU580_REG_BASE_HW_STATUS; in hal_h265e_v580_send_regs()
2268 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &cfg1); in hal_h265e_v580_send_regs()
2274 cfg1.reg = &reg_out->st; in hal_h265e_v580_send_regs()
2275 cfg1.size = sizeof(H265eV580StatusElem) - 4; in hal_h265e_v580_send_regs()
2276 cfg1.offset = VEPU580_STATUS_OFFSET; in hal_h265e_v580_send_regs()
2278 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &cfg1); in hal_h265e_v580_send_regs()