1686         MppDevRegRdCfg cfg1;  in hal_h265e_v540_start()  local
1717         cfg1.reg = &reg_out->hw_status;  in hal_h265e_v540_start()
1718         cfg1.size = sizeof(RK_U32);  in hal_h265e_v540_start()
1719         cfg1.offset = VEPU541_REG_BASE_HW_STATUS;  in hal_h265e_v540_start()
1721         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);  in hal_h265e_v540_start()
1727         cfg1.reg = &reg_out->st_bsl;  in hal_h265e_v540_start()
1728         cfg1.size = sizeof(H265eV541IoctlOutputElem) - 4;  in hal_h265e_v540_start()
1729         cfg1.offset = VEPU541_REG_BASE_STATISTICS;  in hal_h265e_v540_start()
1731         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);  in hal_h265e_v540_start()
1808         MppDevRegRdCfg cfg1;  in hal_h265e_v541_start()  local
1810         cfg1.reg = &reg_out->hw_status;  in hal_h265e_v541_start()
1811         cfg1.size = sizeof(RK_U32);  in hal_h265e_v541_start()
1812         cfg1.offset = VEPU541_REG_BASE_HW_STATUS;  in hal_h265e_v541_start()
1814         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);  in hal_h265e_v541_start()
1820         cfg1.reg = &reg_out->st_bsl;  in hal_h265e_v541_start()
1821         cfg1.size = sizeof(H265eV541IoctlOutputElem) - 4;  in hal_h265e_v541_start()
1822         cfg1.offset = VEPU541_REG_BASE_STATISTICS;  in hal_h265e_v541_start()
1824         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);  in hal_h265e_v541_start()