| /rk3399_rockchip-uboot/board/imgtec/malta/ |
| H A D | lowlevel_init.S | 177 sw zero, MSC01_PCI_P2SCMAPL_OFS(t0)
193 sw zero, MSC01_PCI_HEAD3_OFS(t0)
194 sw zero, MSC01_PCI_HEAD4_OFS(t0)
195 sw zero, MSC01_PCI_HEAD5_OFS(t0)
196 sw zero, MSC01_PCI_HEAD6_OFS(t0)
197 sw zero, MSC01_PCI_HEAD7_OFS(t0)
198 sw zero, MSC01_PCI_HEAD8_OFS(t0)
199 sw zero, MSC01_PCI_HEAD9_OFS(t0)
200 sw zero, MSC01_PCI_HEAD10_OFS(t0)
201 sw zero, MSC01_PCI_HEAD12_OFS(t0)
[all …]
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| /rk3399_rockchip-uboot/arch/mips/lib/ |
| H A D | cache_init.S | 60 move \sz, zero
122 move R_L2_SIZE, zero
123 move R_L2_LINE, zero
124 move R_L2_BYPASSED, zero
125 move R_L2_L2C, zero
178 sw zero, GCR_L2_TAG_ADDR(t0)
179 sw zero, GCR_L2_TAG_ADDR_UPPER(t0)
180 sw zero, GCR_L2_TAG_STATE(t0)
181 sw zero, GCR_L2_TAG_STATE_UPPER(t0)
182 sw zero, GCR_L2_DATA(t0)
[all …]
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| /rk3399_rockchip-uboot/arch/mips/cpu/ |
| H A D | start.S | 40 MTC0 zero, CP0_WATCHLO,\sel
74 PTR_S zero, 0(t0)
86 mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
206 MTC0 zero, CP0_WATCHLO
207 mtc0 zero, CP0_WATCHHI
211 mtc0 zero, CP0_CAUSE
214 mtc0 zero, CP0_COMPARE
275 move a0, zero # a0 <-- boot_flags = 0
279 move ra, zero
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| /rk3399_rockchip-uboot/board/dbau1x00/ |
| H A D | lowlevel_init.S | 55 beq zero,t1,big_endian
95 mtc0 zero, CP0_PERFORMANCE
101 mtc0 zero, CP0_DEBUG
112 mtc0 zero, CP0_WIRED
172 beq zero, t3, tlbloop
177 mtc0 zero, CP0_ENTRYLO0
178 mtc0 zero, CP0_ENTRYLO1
179 mtc0 zero, CP0_PAGEMASK
201 bne t1, zero, 1b
414 bne t1, zero, 1b
[all …]
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| /rk3399_rockchip-uboot/board/pb1x00/ |
| H A D | lowlevel_init.S | 49 bne t2, zero, big_endian
90 mtc0 zero, CP0_PERFORMANCE
96 mtc0 zero, CP0_DEBUG
107 mtc0 zero, CP0_WIRED
122 bne t1, zero, 1b
290 bne t1, zero, 1b
338 sw zero, 0(t0)
342 sw zero, 0(t0)
344 sw zero, 0(t0)
370 bne t1, zero, 1b
|
| /rk3399_rockchip-uboot/arch/mips/include/asm/ |
| H A D | regdef.h | 20 #define zero $0 /* wired zero */ macro
63 #define zero $0 /* wired zero */ macro
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| /rk3399_rockchip-uboot/cmd/ |
| H A D | tpm_test.c | 197 uint32_t zero = 0; in test_global_lock() local
207 TPM_CHECK(tpm_nv_write_value(INDEX0, (uint8_t *)&zero, in test_global_lock()
210 TPM_CHECK(tpm_nv_write_value(INDEX1, (uint8_t *)&zero, in test_global_lock()
251 uint32_t zero = 0; in initialise_spaces() local
257 tpm_nv_write_value(INDEX0, (uint8_t *)&zero, 4); in initialise_spaces()
259 tpm_nv_write_value(INDEX1, (uint8_t *)&zero, 4); in initialise_spaces()
261 tpm_nv_write_value(INDEX2, (uint8_t *)&zero, 4); in initialise_spaces()
263 tpm_nv_write_value(INDEX3, (uint8_t *)&zero, 4); in initialise_spaces()
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| /rk3399_rockchip-uboot/board/Seagate/nas220/ |
| H A D | kwbimage.cfg | 29 # bit23-14: zero
32 # bit29-26: zero
61 # bit31-13: zero required
94 # bit12: 0, PD must be zero
140 # bit31-4: zero, required
|
| /rk3399_rockchip-uboot/board/Marvell/guruplug/ |
| H A D | kwbimage.cfg | 26 # bit23-14: zero
29 # bit29-26: zero
59 # bit31-13: zero required
91 # bit12: 0, PD must be zero
139 # bit31-4: zero, required
|
| /rk3399_rockchip-uboot/board/Seagate/dockstar/ |
| H A D | kwbimage.cfg | 29 # bit23-14: zero
32 # bit29-26: zero
62 # bit31-13: zero required
94 # bit12: 0, PD must be zero
142 # bit31-4: zero, required
|
| /rk3399_rockchip-uboot/board/Synology/ds109/ |
| H A D | kwbimage.cfg | 30 # bit23-14: zero
33 # bit29-26: zero
63 # bit31-13: zero required
95 # bit12: 0, PD must be zero
145 # bit31-4: zero, required
|
| /rk3399_rockchip-uboot/board/Marvell/dreamplug/ |
| H A D | kwbimage.cfg | 27 # bit23-14: zero
30 # bit29-26: zero
60 # bit31-13: zero required
92 # bit12: 0, PD must be zero
140 # bit31-4: zero, required
|
| /rk3399_rockchip-uboot/board/Seagate/goflexhome/ |
| H A D | kwbimage.cfg | 32 # bit23-14: zero
35 # bit29-26: zero
65 # bit31-13: zero required
97 # bit12: 0, PD must be zero
145 # bit31-4: zero, required
|
| /rk3399_rockchip-uboot/board/Marvell/sheevaplug/ |
| H A D | kwbimage.cfg | 26 # bit23-14: zero
29 # bit29-26: zero
59 # bit31-13: zero required
91 # bit12: 0, PD must be zero
139 # bit31-4: zero, required
|
| /rk3399_rockchip-uboot/arch/mips/mach-pic32/ |
| H A D | lowlevel_init.S | 22 mtc0 zero, CP0_WIRED
|
| /rk3399_rockchip-uboot/board/LaCie/netspace_v2/ |
| H A D | kwbimage.cfg | 27 # bit23-14: zero
30 # bit29-26: zero
59 # bit31-13: zero required
91 # bit12: 0, PD must be zero
140 # bit31-4: zero, required
|
| H A D | kwbimage-is2.cfg | 27 # bit23-14: zero
30 # bit29-26: zero
59 # bit31-13: zero required
91 # bit12: 0, PD must be zero
140 # bit31-4: zero, required
|
| H A D | kwbimage-ns2l.cfg | 27 # bit23-14: zero
30 # bit29-26: zero
59 # bit31-13: zero required
91 # bit12: 0, PD must be zero
140 # bit31-4: zero, required
|
| /rk3399_rockchip-uboot/board/cloudengines/pogo_e02/ |
| H A D | kwbimage.cfg | 30 # bit23-14: zero
33 # bit29-26: zero
63 # bit31-13: zero required
95 # bit12: 0, PD must be zero
148 # bit31-4: zero, required
|
| /rk3399_rockchip-uboot/board/LaCie/net2big_v2/ |
| H A D | kwbimage.cfg | 27 # bit23-14: zero
30 # bit29-26: zero
59 # bit31-13: zero required
91 # bit12: 0, PD must be zero
140 # bit31-4: zero, required
|
| /rk3399_rockchip-uboot/board/qemu-mips/ |
| H A D | lowlevel_init.S | 36 mtc0 zero, CP0_WIRED
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| /rk3399_rockchip-uboot/configs/ |
| H A D | LicheePi_Zero_defconfig | 6 CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
|
| H A D | orangepi_zero_defconfig | 8 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero"
|
| H A D | orangepi_zero_plus2_defconfig | 8 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus2"
|
| /rk3399_rockchip-uboot/board/keymile/km_arm/ |
| H A D | kwbimage.cfg | 46 # bit23-14: zero
49 # bit29-26: zero
80 # bit31-13: zero required
151 # bit31-4: zero, required
|