10764c164SVlad Lungu/* Memory sub-system initialization code */ 20764c164SVlad Lungu 30764c164SVlad Lungu#include <config.h> 40764c164SVlad Lungu#include <asm/regdef.h> 50764c164SVlad Lungu#include <asm/mipsregs.h> 60764c164SVlad Lungu 70764c164SVlad Lungu .text 80764c164SVlad Lungu .set noreorder 90764c164SVlad Lungu .set mips32 100764c164SVlad Lungu 110764c164SVlad Lungu .globl lowlevel_init 120764c164SVlad Lungulowlevel_init: 130764c164SVlad Lungu 140764c164SVlad Lungu /* 150764c164SVlad Lungu * Step 2) Establish Status Register 160764c164SVlad Lungu * (set BEV, clear ERL, clear EXL, clear IE) 170764c164SVlad Lungu */ 180764c164SVlad Lungu li t1, 0x00400000 190764c164SVlad Lungu mtc0 t1, CP0_STATUS 200764c164SVlad Lungu 210764c164SVlad Lungu /* 220764c164SVlad Lungu * Step 3) Establish CP0 Config0 230764c164SVlad Lungu * (set K0=3) 240764c164SVlad Lungu */ 250764c164SVlad Lungu li t1, 0x00000003 260764c164SVlad Lungu mtc0 t1, CP0_CONFIG 270764c164SVlad Lungu 280764c164SVlad Lungu /* 290764c164SVlad Lungu * Step 7) Establish Cause 300764c164SVlad Lungu * (set IV bit) 310764c164SVlad Lungu */ 320764c164SVlad Lungu li t1, 0x00800000 330764c164SVlad Lungu mtc0 t1, CP0_CAUSE 340764c164SVlad Lungu 350764c164SVlad Lungu /* Establish Wired (and Random) */ 360764c164SVlad Lungu mtc0 zero, CP0_WIRED 370764c164SVlad Lungu nop 380764c164SVlad Lungu 39*43c50925SShinya Kuribayashi jr ra 400764c164SVlad Lungu nop 41