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Searched refs:writeb (Results 1 – 25 of 107) sorted by relevance

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/rk3399_rockchip-uboot/board/astro/mcf5373l/
H A Dfpga.c40 writeb(tmp_char, &gpiop->par_timer); in altera_pre_fn()
48 writeb(0x00, &gpiop->par_pwm); in altera_pre_fn()
50 writeb(0x01, &gpiop->pddr_timer); in altera_pre_fn()
51 writeb(0x25, &gpiop->pddr_qspi); in altera_pre_fn()
52 writeb(0x0c, &gpiop->pddr_uart); in altera_pre_fn()
53 writeb(0x04, &gpiop->pddr_pwm); in altera_pre_fn()
56 writeb(0x08, &gpiop->ppd_uart); in altera_pre_fn()
57 writeb(0x38, &gpiop->ppd_qspi); in altera_pre_fn()
60 writeb(0xFB, &gpiop->pclrr_uart); in altera_pre_fn()
62 writeb(0xFE, &gpiop->pclrr_timer); in altera_pre_fn()
[all …]
H A Dmcf5373l.c111 writeb(UART_UCR_RESET_RX, &uart->ucr); in rs_serial_init()
112 writeb(UART_UCR_RESET_TX, &uart->ucr); in rs_serial_init()
113 writeb(UART_UCR_RESET_ERROR, &uart->ucr); in rs_serial_init()
114 writeb(UART_UCR_RESET_MR, &uart->ucr); in rs_serial_init()
117 writeb(0, &uart->uimr); in rs_serial_init()
120 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); in rs_serial_init()
122 writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); in rs_serial_init()
123 writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); in rs_serial_init()
130 writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1); in rs_serial_init()
132 writeb((u8) (counter & 0x00ff), &uart->ubg2); in rs_serial_init()
[all …]
/rk3399_rockchip-uboot/drivers/serial/
H A Dmcfuart.c35 writeb(UART_UCR_RESET_RX, &uart->ucr); in mcf_serial_init_common()
36 writeb(UART_UCR_RESET_TX, &uart->ucr); in mcf_serial_init_common()
37 writeb(UART_UCR_RESET_ERROR, &uart->ucr); in mcf_serial_init_common()
38 writeb(UART_UCR_RESET_MR, &uart->ucr); in mcf_serial_init_common()
41 writeb(0, &uart->uimr); in mcf_serial_init_common()
44 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); in mcf_serial_init_common()
46 writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); in mcf_serial_init_common()
47 writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); in mcf_serial_init_common()
54 writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1); in mcf_serial_init_common()
56 writeb((u8)(counter & 0x00ff), &uart->ubg2); in mcf_serial_init_common()
[all …]
/rk3399_rockchip-uboot/drivers/ata/
H A Dsata_sil3114.c64 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
66 writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
68 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
120 writeb (cmd, port[num].ioaddr.command_addr); in sata_identify()
186 writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr); in set_Feature_cmd()
187 writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr); in set_Feature_cmd()
188 writeb (0, port[num].ioaddr.lbal_addr); in set_Feature_cmd()
189 writeb (0, port[num].ioaddr.lbam_addr); in set_Feature_cmd()
190 writeb (0, port[num].ioaddr.lbah_addr); in set_Feature_cmd()
192 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr); in set_Feature_cmd()
[all …]
H A Dmxc_ata.c95 writeb(3, &ata_regs->time_off); in set_ata_bus_timing()
96 writeb(3, &ata_regs->time_on); in set_ata_bus_timing()
97 writeb((pio_t1[mode] + T) / T, &ata_regs->time_1); in set_ata_bus_timing()
98 writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2w); in set_ata_bus_timing()
101 writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2r); in set_ata_bus_timing()
102 writeb((pio_tA[mode] + T) / T + 2, &ata_regs->time_ax); in set_ata_bus_timing()
103 writeb(1, &ata_regs->time_pio_rdx); in set_ata_bus_timing()
104 writeb((pio_t4[mode] + T) / T, &ata_regs->time_4); in set_ata_bus_timing()
107 writeb((pio_t9[mode] + T) / T, &ata_regs->time_9); in set_ata_bus_timing()
/rk3399_rockchip-uboot/drivers/usb/musb/
H A Dmusb_core.c30 writeb(0, &musbr->intrusbe); in musb_start()
31 writeb(0, &musbr->testmode); in musb_start()
34 writeb(MUSB_POWER_HSENAB, &musbr->power); in musb_start()
43 writeb(devctl | MUSB_DEVCTL_SESSION, &musbr->devctl); in musb_start()
52 writeb(idx, &musbr->dir##fifosz); \
78 writeb(epinfo->epnum, &musbr->index); in musb_configure_ep()
124 writeb(ep, &musbr->index); in write_fifo()
128 writeb(*data++, &musbr->fifox[ep]); in write_fifo()
149 writeb(ep, &musbr->index); in read_fifo()
H A Dmusb_hcd.c422 writeb(hub, &musbr->tar[ep].txhubaddr); in config_hub_port()
423 writeb((chid + 1), &musbr->tar[ep].txhubport); in config_hub_port()
424 writeb(hub, &musbr->tar[ep].rxhubaddr); in config_hub_port()
425 writeb((chid + 1), &musbr->tar[ep].rxhubport); in config_hub_port()
437 writeb(power | MUSB_POWER_RESET, &musbr->power); in musb_port_reset()
442 writeb(power & ~MUSB_POWER_RESET, &musbr->power); in musb_port_reset()
769 writeb(MUSB_CONTROL_EP, &musbr->index); in submit_control_msg()
774 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr); in submit_control_msg()
775 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr); in submit_control_msg()
783 writeb(devspeed << 6, &musbr->txtype); in submit_control_msg()
[all …]
/rk3399_rockchip-uboot/drivers/rtc/
H A Ds3c24x0_rtc.c35 writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon); in SetRTC_Access()
39 writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon); in SetRTC_Access()
132 writeb(sec, &rtc->bcdsec); in rtc_set()
133 writeb(min, &rtc->bcdmin); in rtc_set()
134 writeb(hour, &rtc->bcdhour); in rtc_set()
135 writeb(mday, &rtc->bcddate); in rtc_set()
136 writeb(wday, &rtc->bcdday); in rtc_set()
137 writeb(mon, &rtc->bcdmon); in rtc_set()
138 writeb(year, &rtc->bcdyear); in rtc_set()
150 writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon); in rtc_reset()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm1136/mx35/
H A Dmx35_sdram.c90 writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */ in mx3_setup_sdram_bank()
91 writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */ in mx3_setup_sdram_bank()
92 writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ in mx3_setup_sdram_bank()
93 writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */ in mx3_setup_sdram_bank()
108 writeb(0xda, start_address + ESDCTL_DDR2_MR); in mx3_setup_sdram_bank()
109 writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT); in mx3_setup_sdram_bank()
112 writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ in mx3_setup_sdram_bank()
/rk3399_rockchip-uboot/drivers/i2c/
H A Dfsl_i2c.c180 writeb(dfsr, &base->dfsrr); /* set default filter */ in set_i2c_bus_speed()
181 writeb(fdr, &base->fdr); /* set bus speed */ in set_i2c_bus_speed()
191 writeb(fdr, &base->fdr); /* set bus speed */ in set_i2c_bus_speed()
223 writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr); in fsl_i2c_fixup()
233 writeb(0, &base->cr); in fsl_i2c_fixup()
235 writeb(I2C_CR_MSTA | flags, &base->cr); in fsl_i2c_fixup()
236 writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr); in fsl_i2c_fixup()
249 writeb(I2C_CR_MEN | flags, &base->cr); in fsl_i2c_fixup()
250 writeb(0, &base->sr); in fsl_i2c_fixup()
269 writeb(0, &base->cr); /* stop I2C controller */ in __i2c_init()
[all …]
H A Dsh_i2c.c113 writeb(iccl & 0xff, &dev->iccl); in sh_i2c_set_addr()
114 writeb(icch & 0xff, &dev->icch); in sh_i2c_set_addr()
121 writeb(icic, &dev->icic); in sh_i2c_set_addr()
123 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); in sh_i2c_set_addr()
127 writeb(chip << 1, &dev->icdr); in sh_i2c_set_addr()
131 writeb(addr, &dev->icdr); in sh_i2c_set_addr()
133 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr); in sh_i2c_set_addr()
142 writeb(0, &dev->icsr); in sh_i2c_finish()
154 writeb(val, &dev->icdr); in sh_i2c_raw_write()
158 writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr); in sh_i2c_raw_write()
[all …]
H A Dmxc_i2c.c182 writeb(idx, base + (IFDR << reg_shift)); in bus_i2c_set_bus_speed()
185 writeb(I2CR_IDIS, base + (I2CR << reg_shift)); in bus_i2c_set_bus_speed()
186 writeb(0, base + (I2SR << reg_shift)); in bus_i2c_set_bus_speed()
206 writeb(sr | I2SR_IAL, base + in wait_for_sr_state()
209 writeb(sr & ~I2SR_IAL, base + in wait_for_sr_state()
235 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); in tx_byte()
236 writeb(byte, base + (I2DR << reg_shift)); in tx_byte()
267 writeb(temp, base + (I2CR << reg_shift)); in i2c_imx_stop()
296 writeb(I2CR_IEN, base + (I2CR << reg_shift)); in i2c_init_transfer_()
302 writeb((chip << 1) ^ 2, base + (IADR << reg_shift)); in i2c_init_transfer_()
[all …]
/rk3399_rockchip-uboot/drivers/spi/
H A Dsh_qspi.c84 writeb(SPCR_MSTR, &ss->regs->spcr); in sh_qspi_init()
87 writeb(0x00, &ss->regs->sslp); in sh_qspi_init()
90 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr); in sh_qspi_init()
93 writeb(0x01, &ss->regs->spbr); in sh_qspi_init()
96 writeb(0x00, &ss->regs->spdcr); in sh_qspi_init()
99 writeb(0x00, &ss->regs->spckd); in sh_qspi_init()
102 writeb(0x00, &ss->regs->sslnd); in sh_qspi_init()
105 writeb(0x00, &ss->regs->spnd); in sh_qspi_init()
117 writeb(0x00, &ss->regs->spscr); in sh_qspi_init()
133 writeb(SPCR_MSTR, &ss->regs->spcr); in spi_cs_activate()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap3/
H A Dspl_id_nand.c39 writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
40 writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
47 writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
50 writeb(0x0, &gpmc_cfg->cs[0].nand_adr); in identify_nand_chip()
/rk3399_rockchip-uboot/drivers/watchdog/
H A Dulp_wdog.c71 writeb(val, &wdog->cs2); in hw_watchdog_init()
76 writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ in hw_watchdog_init()
77 writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */ in hw_watchdog_init()
92 writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ in reset_cpu()
93 writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */ in reset_cpu()
/rk3399_rockchip-uboot/board/freescale/s32v234evb/
H A Dclock.c249 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL58); in enable_modules_clock()
251 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL170); in enable_modules_clock()
253 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL83); in enable_modules_clock()
255 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL188); in enable_modules_clock()
257 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL50); in enable_modules_clock()
259 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL93); in enable_modules_clock()
261 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL81); in enable_modules_clock()
263 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL184); in enable_modules_clock()
265 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL186); in enable_modules_clock()
267 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL54); in enable_modules_clock()
[all …]
/rk3399_rockchip-uboot/arch/sh/cpu/sh2/
H A Dcpu.c15 writeb(readb(STBCR4) & ~0x04, STBCR4);\
18 writeb(readb(STBCR4) & ~0x80, STBCR4);\
21 writeb(readb(STBCR4) & ~0x10, STBCR4);\
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mxs/
H A Dclock.c167 writeb(CLKCTRL_FRAC_CLKGATE, in mxs_set_ioclk()
169 writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK), in mxs_set_ioclk()
171 writeb(CLKCTRL_FRAC_CLKGATE, in mxs_set_ioclk()
371 writeb(CLKCTRL_FRAC_CLKGATE, in mxs_set_lcdclk()
373 writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK), in mxs_set_lcdclk()
375 writeb(CLKCTRL_FRAC_CLKGATE, in mxs_set_lcdclk()
387 writeb(CLKCTRL_FRAC_CLKGATE, in mxs_set_lcdclk()
389 writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK), in mxs_set_lcdclk()
391 writeb(CLKCTRL_FRAC_CLKGATE, in mxs_set_lcdclk()
H A Dspl_mem_init.c157 writeb(CLKCTRL_FRAC_CLKGATE, in mxs_mem_init_clock()
161 writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK), in mxs_mem_init_clock()
165 writeb(CLKCTRL_FRAC_CLKGATE, in mxs_mem_init_clock()
192 writeb(19 & CLKCTRL_FRAC_FRAC_MASK, in mxs_mem_setup_cpu_and_hbus()
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap4/
H A Dboot.c88 writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET)); in omap_reboot_mode_clear()
98 writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE + in omap_reboot_mode_store()
101 writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE + in omap_reboot_mode_store()
/rk3399_rockchip-uboot/board/renesas/sh7785lcr/
H A Dselfcheck.c37 writeb(0x55, PLD_LEDCR); in test_led()
40 writeb(0xaa, PLD_LEDCR); in test_led()
42 writeb(0x00, PLD_LEDCR); in test_led()
/rk3399_rockchip-uboot/board/h2200/
H A Dh2200.c27 writeb(0x1, 0x4000); in reset_cpu()
30 writeb(0xff, 0x4002); in reset_cpu()
/rk3399_rockchip-uboot/board/isee/igep00x0/
H A Dcommon.c40 writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); in board_init()
41 writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); in board_init()
/rk3399_rockchip-uboot/drivers/gpio/
H A Dhi6220_gpio.c21 writeb(data, bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_input()
31 writeb(!!value << gpio, bank->base + (BIT(gpio + 2))); in hi6220_gpio_set_value()
43 writeb(data, bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_output()
/rk3399_rockchip-uboot/arch/sh/lib/
H A Dtime.c38 writeb(readb(&tmu->tstr) | (1 << timer), &tmu->tstr); in tmu_timer_start()
45 writeb(readb(&tmu->tstr) & ~(1 << timer), &tmu->tstr); in tmu_timer_stop()

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