1*983e3700STom Rini /*
2*983e3700STom Rini * OMAP4 boot
3*983e3700STom Rini *
4*983e3700STom Rini * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
5*983e3700STom Rini *
6*983e3700STom Rini * SPDX-License-Identifier: GPL-2.0+
7*983e3700STom Rini */
8*983e3700STom Rini
9*983e3700STom Rini #include <common.h>
10*983e3700STom Rini #include <asm/io.h>
11*983e3700STom Rini #include <asm/omap_common.h>
12*983e3700STom Rini #include <asm/arch/sys_proto.h>
13*983e3700STom Rini #include <spl.h>
14*983e3700STom Rini
15*983e3700STom Rini static u32 boot_devices[] = {
16*983e3700STom Rini BOOT_DEVICE_MMC2,
17*983e3700STom Rini BOOT_DEVICE_XIP,
18*983e3700STom Rini BOOT_DEVICE_XIPWAIT,
19*983e3700STom Rini BOOT_DEVICE_NAND,
20*983e3700STom Rini BOOT_DEVICE_XIPWAIT,
21*983e3700STom Rini BOOT_DEVICE_MMC1,
22*983e3700STom Rini BOOT_DEVICE_ONENAND,
23*983e3700STom Rini BOOT_DEVICE_ONENAND,
24*983e3700STom Rini BOOT_DEVICE_MMC2,
25*983e3700STom Rini BOOT_DEVICE_ONENAND,
26*983e3700STom Rini BOOT_DEVICE_XIPWAIT,
27*983e3700STom Rini BOOT_DEVICE_NAND,
28*983e3700STom Rini BOOT_DEVICE_NAND,
29*983e3700STom Rini BOOT_DEVICE_MMC1,
30*983e3700STom Rini BOOT_DEVICE_ONENAND,
31*983e3700STom Rini BOOT_DEVICE_MMC2,
32*983e3700STom Rini BOOT_DEVICE_XIP,
33*983e3700STom Rini BOOT_DEVICE_XIPWAIT,
34*983e3700STom Rini BOOT_DEVICE_NAND,
35*983e3700STom Rini BOOT_DEVICE_MMC1,
36*983e3700STom Rini BOOT_DEVICE_MMC1,
37*983e3700STom Rini BOOT_DEVICE_ONENAND,
38*983e3700STom Rini BOOT_DEVICE_MMC2,
39*983e3700STom Rini BOOT_DEVICE_XIP,
40*983e3700STom Rini BOOT_DEVICE_MMC2_2,
41*983e3700STom Rini BOOT_DEVICE_NAND,
42*983e3700STom Rini BOOT_DEVICE_MMC2_2,
43*983e3700STom Rini BOOT_DEVICE_MMC1,
44*983e3700STom Rini BOOT_DEVICE_MMC2_2,
45*983e3700STom Rini BOOT_DEVICE_MMC2_2,
46*983e3700STom Rini BOOT_DEVICE_NONE,
47*983e3700STom Rini BOOT_DEVICE_XIPWAIT,
48*983e3700STom Rini };
49*983e3700STom Rini
omap_sys_boot_device(void)50*983e3700STom Rini u32 omap_sys_boot_device(void)
51*983e3700STom Rini {
52*983e3700STom Rini u32 sys_boot;
53*983e3700STom Rini
54*983e3700STom Rini /* Grab the first 5 bits of the status register for SYS_BOOT. */
55*983e3700STom Rini sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 5) - 1);
56*983e3700STom Rini
57*983e3700STom Rini if (sys_boot >= (sizeof(boot_devices) / sizeof(u32)))
58*983e3700STom Rini return BOOT_DEVICE_NONE;
59*983e3700STom Rini
60*983e3700STom Rini return boot_devices[sys_boot];
61*983e3700STom Rini }
62*983e3700STom Rini
omap_reboot_mode(char * mode,unsigned int length)63*983e3700STom Rini int omap_reboot_mode(char *mode, unsigned int length)
64*983e3700STom Rini {
65*983e3700STom Rini unsigned int limit;
66*983e3700STom Rini unsigned int i;
67*983e3700STom Rini
68*983e3700STom Rini if (length < 2)
69*983e3700STom Rini return -1;
70*983e3700STom Rini
71*983e3700STom Rini if (!warm_reset())
72*983e3700STom Rini return -1;
73*983e3700STom Rini
74*983e3700STom Rini limit = (length < OMAP_REBOOT_REASON_SIZE) ? length :
75*983e3700STom Rini OMAP_REBOOT_REASON_SIZE;
76*983e3700STom Rini
77*983e3700STom Rini for (i = 0; i < (limit - 1); i++)
78*983e3700STom Rini mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE +
79*983e3700STom Rini OMAP_REBOOT_REASON_OFFSET + i));
80*983e3700STom Rini
81*983e3700STom Rini mode[i] = '\0';
82*983e3700STom Rini
83*983e3700STom Rini return 0;
84*983e3700STom Rini }
85*983e3700STom Rini
omap_reboot_mode_clear(void)86*983e3700STom Rini int omap_reboot_mode_clear(void)
87*983e3700STom Rini {
88*983e3700STom Rini writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET));
89*983e3700STom Rini
90*983e3700STom Rini return 0;
91*983e3700STom Rini }
92*983e3700STom Rini
omap_reboot_mode_store(char * mode)93*983e3700STom Rini int omap_reboot_mode_store(char *mode)
94*983e3700STom Rini {
95*983e3700STom Rini unsigned int i;
96*983e3700STom Rini
97*983e3700STom Rini for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++)
98*983e3700STom Rini writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE +
99*983e3700STom Rini OMAP_REBOOT_REASON_OFFSET + i));
100*983e3700STom Rini
101*983e3700STom Rini writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE +
102*983e3700STom Rini OMAP_REBOOT_REASON_OFFSET + i));
103*983e3700STom Rini
104*983e3700STom Rini return 0;
105*983e3700STom Rini }
106