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Searched refs:timings (Results 1 – 25 of 77) sorted by relevance

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/rk3399_rockchip-uboot/board/overo/
H A Dspl.c25 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
27 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
30 timings->mcfg = MICRON_V_MCFG_165(256 << 20); in get_board_mem_timings()
31 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
32 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
33 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
37 timings->mcfg = MICRON_V_MCFG_200(256 << 20); in get_board_mem_timings()
38 timings->ctrla = MICRON_V_ACTIMA_200; in get_board_mem_timings()
39 timings->ctrlb = MICRON_V_ACTIMB_200; in get_board_mem_timings()
40 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; in get_board_mem_timings()
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/rk3399_rockchip-uboot/board/isee/igep00x0/
H A Dspl.c16 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
20 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
24 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); in get_board_mem_timings()
25 timings->ctrla = HYNIX_V_ACTIMA_200; in get_board_mem_timings()
26 timings->ctrlb = HYNIX_V_ACTIMB_200; in get_board_mem_timings()
29 timings->mcfg = MICRON_V_MCFG_200(256 << 20); in get_board_mem_timings()
30 timings->ctrla = MICRON_V_ACTIMA_200; in get_board_mem_timings()
31 timings->ctrlb = MICRON_V_ACTIMB_200; in get_board_mem_timings()
37 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; in get_board_mem_timings()
41 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); in get_board_mem_timings()
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/rk3399_rockchip-uboot/arch/arm/mach-imx/
H A Dddrmc-vf610.c108 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, in ddrmc_ctrl_init_ddr3() argument
118 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]); in ddrmc_ctrl_init_ddr3()
119 writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]); in ddrmc_ctrl_init_ddr3()
121 writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]); in ddrmc_ctrl_init_ddr3()
122 writel(DDRMC_CR12_WRLAT(timings->wrlat) | in ddrmc_ctrl_init_ddr3()
123 DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]); in ddrmc_ctrl_init_ddr3()
124 writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) | in ddrmc_ctrl_init_ddr3()
125 DDRMC_CR13_TCCD(timings->tccd) | in ddrmc_ctrl_init_ddr3()
126 DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval), in ddrmc_ctrl_init_ddr3()
128 writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) | in ddrmc_ctrl_init_ddr3()
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/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c103 struct board_sdrc_timings *timings) in write_sdrc_timings() argument
106 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); in write_sdrc_timings()
107 writel(timings->ctrla, &sdrc_actim_base->ctrla); in write_sdrc_timings()
108 writel(timings->ctrlb, &sdrc_actim_base->ctrlb); in write_sdrc_timings()
109 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); in write_sdrc_timings()
114 writel(timings->mr, &sdrc_base->cs[cs].mr); in write_sdrc_timings()
133 struct board_sdrc_timings timings; in do_sdrc_init() local
139 timings.sharing = SDRC_SHARING; in do_sdrc_init()
152 get_board_mem_timings(&timings); in do_sdrc_init()
162 writel(timings.sharing, &sdrc_base->sharing); in do_sdrc_init()
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/rk3399_rockchip-uboot/board/ti/beagle/
H A Dbeagle.c147 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
158 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
163 timings->mcfg = NUMONYX_V_MCFG_165(512 << 20); in get_board_mem_timings()
164 timings->ctrla = NUMONYX_V_ACTIMA_165; in get_board_mem_timings()
165 timings->ctrlb = NUMONYX_V_ACTIMB_165; in get_board_mem_timings()
166 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
170 timings->mcfg = MICRON_V_MCFG_165(128 << 20); in get_board_mem_timings()
171 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
172 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
173 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
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/rk3399_rockchip-uboot/board/quipos/cairo/
H A Dcairo.c70 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
72 timings->sharing = SAMSUNG_SHARING; in get_board_mem_timings()
73 timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20); in get_board_mem_timings()
74 timings->ctrla = SAMSUNG_V_ACTIMA_165; in get_board_mem_timings()
75 timings->ctrlb = SAMSUNG_V_ACTIMB_165; in get_board_mem_timings()
76 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
77 timings->mr = SAMSUNG_V_MR_165; in get_board_mem_timings()
/rk3399_rockchip-uboot/board/corscience/tricorder/
H A Dtricorder.c164 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
172 timings->mcfg = MCFG((256 << 20), 14); in get_board_mem_timings()
182 timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC, in get_board_mem_timings()
192 timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE, in get_board_mem_timings()
195 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
196 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
199 timings->mcfg = MICRON_V_MCFG_165(128 << 20); in get_board_mem_timings()
200 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
201 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
202 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
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/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Dnand_timings.c19 .timings.sdr = {
61 .timings.sdr = {
103 .timings.sdr = {
145 .timings.sdr = {
187 .timings.sdr = {
229 .timings.sdr = {
280 return &onfi_sdr_timings[mode].timings.sdr; in onfi_async_timing_mode_to_sdr_timings()
310 struct nand_sdr_timings *timings = &iface->timings.sdr; in onfi_init_data_interface() local
313 timings->tPROG_max = 1000000ULL * le16_to_cpu(params->t_prog); in onfi_init_data_interface()
314 timings->tBERS_max = 1000000ULL * le16_to_cpu(params->t_bers); in onfi_init_data_interface()
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H A Dsunxi_nand.c1225 const struct nand_sdr_timings *timings) in sunxi_nand_chip_set_timings() argument
1231 if (timings->tCLS_min > min_clk_period) in sunxi_nand_chip_set_timings()
1232 min_clk_period = timings->tCLS_min; in sunxi_nand_chip_set_timings()
1235 if (timings->tCLH_min > min_clk_period) in sunxi_nand_chip_set_timings()
1236 min_clk_period = timings->tCLH_min; in sunxi_nand_chip_set_timings()
1239 if (timings->tCS_min > min_clk_period) in sunxi_nand_chip_set_timings()
1240 min_clk_period = timings->tCS_min; in sunxi_nand_chip_set_timings()
1243 if (timings->tCH_min > min_clk_period) in sunxi_nand_chip_set_timings()
1244 min_clk_period = timings->tCH_min; in sunxi_nand_chip_set_timings()
1247 if (timings->tWP_min > min_clk_period) in sunxi_nand_chip_set_timings()
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H A Ddenali.c947 const struct nand_sdr_timings *timings; in denali_setup_data_interface() local
954 timings = nand_get_sdr_timings(conf); in denali_setup_data_interface()
955 if (IS_ERR(timings)) in denali_setup_data_interface()
956 return PTR_ERR(timings); in denali_setup_data_interface()
976 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x); in denali_setup_data_interface()
985 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x); in denali_setup_data_interface()
994 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x); in denali_setup_data_interface()
1008 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); in denali_setup_data_interface()
1023 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x); in denali_setup_data_interface()
1032 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), in denali_setup_data_interface()
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H A Dstm32_fmc2_nand.c149 struct stm32_fmc2_timings timings; member
183 struct stm32_fmc2_timings *timings = &nand->timings; in stm32_fmc2_timings_init() local
189 pcr |= FMC2_PCR_TCLR(timings->tclr); in stm32_fmc2_timings_init()
191 pcr |= FMC2_PCR_TAR(timings->tar); in stm32_fmc2_timings_init()
194 pmem = FMC2_PMEM_MEMSET(timings->tset_mem); in stm32_fmc2_timings_init()
195 pmem |= FMC2_PMEM_MEMWAIT(timings->twait); in stm32_fmc2_timings_init()
196 pmem |= FMC2_PMEM_MEMHOLD(timings->thold_mem); in stm32_fmc2_timings_init()
197 pmem |= FMC2_PMEM_MEMHIZ(timings->thiz); in stm32_fmc2_timings_init()
200 patt = FMC2_PATT_ATTSET(timings->tset_att); in stm32_fmc2_timings_init()
201 patt |= FMC2_PATT_ATTWAIT(timings->twait); in stm32_fmc2_timings_init()
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/rk3399_rockchip-uboot/board/technexion/tao3530/
H A Dtao3530.c76 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
92 timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */ in get_board_mem_timings()
93 timings->ctrla = HYNIX_V_ACTIMA_165; in get_board_mem_timings()
94 timings->ctrlb = HYNIX_V_ACTIMB_165; in get_board_mem_timings()
97 timings->mcfg = MCFG(128 << 20, 13); /* RAS-width 13 */ in get_board_mem_timings()
98 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
99 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
102 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
103 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
/rk3399_rockchip-uboot/board/timll/devkit8000/
H A Ddevkit8000.c195 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
198 timings->mcfg = MICRON_V_MCFG_165(128 << 20); in get_board_mem_timings()
199 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
202 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
203 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
205 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
/rk3399_rockchip-uboot/board/lg/sniper/
H A Dsniper.c68 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
70 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); in get_board_mem_timings()
71 timings->ctrla = HYNIX_V_ACTIMA_200; in get_board_mem_timings()
72 timings->ctrlb = HYNIX_V_ACTIMB_200; in get_board_mem_timings()
73 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; in get_board_mem_timings()
74 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
/rk3399_rockchip-uboot/board/ti/evm/
H A Devm.c144 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
157 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); in get_board_mem_timings()
158 timings->ctrla = HYNIX_V_ACTIMA_200; in get_board_mem_timings()
159 timings->ctrlb = HYNIX_V_ACTIMB_200; in get_board_mem_timings()
162 timings->mcfg = MICRON_V_MCFG_165(128 << 20); in get_board_mem_timings()
163 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
164 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
166 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
167 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Demif-common.c519 const struct lpddr2_ac_timings *timings = 0; in get_timings_table() local
537 timings = device_timings[i]; in get_timings_table()
541 return timings; in get_timings_table()
596 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings, in get_sdram_tim_1_reg() argument
601 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; in get_sdram_tim_1_reg()
605 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) / in get_sdram_tim_1_reg()
608 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; in get_sdram_tim_1_reg()
612 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; in get_sdram_tim_1_reg()
615 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1; in get_sdram_tim_1_reg()
618 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; in get_sdram_tim_1_reg()
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/rk3399_rockchip-uboot/doc/device-tree-bindings/video/
H A Datmel-hlcdc.txt14 - display-timings: please refer the displaymode.txt.
29 display-timings {
H A Ddisplay-timing.txt4 display-timings node
46 for displays. If a display supports multiple signal timings, the native-mode
77 display-timings {
H A Dtegra20-dc.txt26 - nvidia,panel-timings: 4 cells containing required timings in ms:
84 nvidia,panel-timings = <400 4 203 17 15>;
H A Drockchip-lvds.txt22 - display-timings : described by
64 display-timings {
/rk3399_rockchip-uboot/arch/x86/cpu/quark/
H A Ddram.c38 memcpy(&mrc_params->timings, cache->data, cache->data_size); in prepare_mrc_cache()
156 memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings)); in dram_init()
/rk3399_rockchip-uboot/arch/arm/mach-at91/include/mach/
H A Dsama5d3_smc.h24 u32 timings; /* 0x60C SMC Cycle Register */ member
/rk3399_rockchip-uboot/drivers/video/drm/
H A Dsamsung_mipi_dcphy.c1266 const struct samsung_mipi_dphy_timing *timings; in samsung_mipi_dphy_get_timing() local
1271 timings = samsung_mipi_dphy_timing_table; in samsung_mipi_dphy_get_timing()
1275 if (lane_mbps <= timings[i - 1].max_lane_mbps) in samsung_mipi_dphy_get_timing()
1281 return &timings[i - 1]; in samsung_mipi_dphy_get_timing()
1287 const struct samsung_mipi_cphy_timing *timings; in samsung_mipi_cphy_get_timing() local
1292 timings = samsung_mipi_cphy_timing_table; in samsung_mipi_cphy_get_timing()
1296 if (lane_msps <= timings[i - 1].max_lane_msps) in samsung_mipi_cphy_get_timing()
1302 return &timings[i - 1]; in samsung_mipi_cphy_get_timing()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dtegra20-medcom-wide.dts66 nvidia,panel-timings = <0 0 0 0>;
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap3/
H A Dsys_proto.h42 void get_board_mem_timings(struct board_sdrc_timings *timings);

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