xref: /rk3399_rockchip-uboot/board/quipos/cairo/cairo.c (revision 4125bbcef6a998ce8580a1f5c53c8c93a56a125b)
1d275c40cSAlbert ARIBAUD \(3ADEV\) /*
2d275c40cSAlbert ARIBAUD \(3ADEV\)  * Copyright (c) 2014 DENX
3d275c40cSAlbert ARIBAUD \(3ADEV\)  * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
4d275c40cSAlbert ARIBAUD \(3ADEV\)  *
5d275c40cSAlbert ARIBAUD \(3ADEV\)  * Derived from code written by Robert Aigner (ra@spiid.net)
6d275c40cSAlbert ARIBAUD \(3ADEV\)  *
7d275c40cSAlbert ARIBAUD \(3ADEV\)  * Itself derived from Beagle Board and 3430 SDP code by
8d275c40cSAlbert ARIBAUD \(3ADEV\)  *	Richard Woodruff <r-woodruff2@ti.com>
9d275c40cSAlbert ARIBAUD \(3ADEV\)  *	Syed Mohammed Khasim <khasim@ti.com>
10d275c40cSAlbert ARIBAUD \(3ADEV\)  *
11d275c40cSAlbert ARIBAUD \(3ADEV\)  * SPDX-License-Identifier:	GPL-2.0+
12d275c40cSAlbert ARIBAUD \(3ADEV\)  */
13d275c40cSAlbert ARIBAUD \(3ADEV\) #include <common.h>
14d275c40cSAlbert ARIBAUD \(3ADEV\) #include <dm.h>
15d275c40cSAlbert ARIBAUD \(3ADEV\) #include <netdev.h>
16d275c40cSAlbert ARIBAUD \(3ADEV\) #include <ns16550.h>
17d275c40cSAlbert ARIBAUD \(3ADEV\) #include <asm/io.h>
18d275c40cSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/mem.h>
19d275c40cSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/mux.h>
20d275c40cSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/sys_proto.h>
21d275c40cSAlbert ARIBAUD \(3ADEV\) #include <i2c.h>
22d275c40cSAlbert ARIBAUD \(3ADEV\) #include <asm/mach-types.h>
23d275c40cSAlbert ARIBAUD \(3ADEV\) #include <asm/omap_mmc.h>
24d275c40cSAlbert ARIBAUD \(3ADEV\) #include "cairo.h"
25d275c40cSAlbert ARIBAUD \(3ADEV\) 
26d275c40cSAlbert ARIBAUD \(3ADEV\) DECLARE_GLOBAL_DATA_PTR;
27d275c40cSAlbert ARIBAUD \(3ADEV\) 
28d275c40cSAlbert ARIBAUD \(3ADEV\) /*
29d275c40cSAlbert ARIBAUD \(3ADEV\)  * Routine: board_init
30d275c40cSAlbert ARIBAUD \(3ADEV\)  * Description: Early hardware init.
31d275c40cSAlbert ARIBAUD \(3ADEV\)  */
board_init(void)32d275c40cSAlbert ARIBAUD \(3ADEV\) int board_init(void)
33d275c40cSAlbert ARIBAUD \(3ADEV\) {
34d275c40cSAlbert ARIBAUD \(3ADEV\) 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
35d275c40cSAlbert ARIBAUD \(3ADEV\) 	/* board id for Linux */
36cd7b6344STom Rini 	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
37d275c40cSAlbert ARIBAUD \(3ADEV\) 	/* boot param addr */
38d275c40cSAlbert ARIBAUD \(3ADEV\) 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
39d275c40cSAlbert ARIBAUD \(3ADEV\) 	return 0;
40d275c40cSAlbert ARIBAUD \(3ADEV\) }
41d275c40cSAlbert ARIBAUD \(3ADEV\) 
42d275c40cSAlbert ARIBAUD \(3ADEV\) /*
43d275c40cSAlbert ARIBAUD \(3ADEV\)  * Routine: set_muxconf_regs
44d275c40cSAlbert ARIBAUD \(3ADEV\)  * Description: Setting up the configuration Mux registers specific to the
45d275c40cSAlbert ARIBAUD \(3ADEV\)  *		hardware. Many pins need to be moved from protect to primary
46d275c40cSAlbert ARIBAUD \(3ADEV\)  *		mode.
47d275c40cSAlbert ARIBAUD \(3ADEV\)  */
set_muxconf_regs(void)48d275c40cSAlbert ARIBAUD \(3ADEV\) void set_muxconf_regs(void)
49d275c40cSAlbert ARIBAUD \(3ADEV\) {
50d275c40cSAlbert ARIBAUD \(3ADEV\) 	MUX_CAIRO();
51d275c40cSAlbert ARIBAUD \(3ADEV\) }
52d275c40cSAlbert ARIBAUD \(3ADEV\) 
53*4aa2ba3aSMasahiro Yamada #if defined(CONFIG_MMC)
board_mmc_init(bd_t * bis)54d275c40cSAlbert ARIBAUD \(3ADEV\) int board_mmc_init(bd_t *bis)
55d275c40cSAlbert ARIBAUD \(3ADEV\) {
56d275c40cSAlbert ARIBAUD \(3ADEV\) 	return omap_mmc_init(0, 0, 0, -1, -1);
57d275c40cSAlbert ARIBAUD \(3ADEV\) }
58d275c40cSAlbert ARIBAUD \(3ADEV\) #endif
59d275c40cSAlbert ARIBAUD \(3ADEV\) 
60d275c40cSAlbert ARIBAUD \(3ADEV\) #ifdef CONFIG_SPL_BUILD
61d275c40cSAlbert ARIBAUD \(3ADEV\) /*
62d275c40cSAlbert ARIBAUD \(3ADEV\)  * Routine: get_board_mem_timings
63d275c40cSAlbert ARIBAUD \(3ADEV\)  * Description: If we use SPL then there is no x-loader nor config header
64d275c40cSAlbert ARIBAUD \(3ADEV\)  * so we have to setup the DDR timings ourself on the first bank.  This
65d275c40cSAlbert ARIBAUD \(3ADEV\)  * provides the timing values back to the function that configures
66d275c40cSAlbert ARIBAUD \(3ADEV\)  * the memory.
67d275c40cSAlbert ARIBAUD \(3ADEV\)  *
68d275c40cSAlbert ARIBAUD \(3ADEV\)  * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
69d275c40cSAlbert ARIBAUD \(3ADEV\)  */
get_board_mem_timings(struct board_sdrc_timings * timings)70d275c40cSAlbert ARIBAUD \(3ADEV\) void get_board_mem_timings(struct board_sdrc_timings *timings)
71d275c40cSAlbert ARIBAUD \(3ADEV\) {
72d275c40cSAlbert ARIBAUD \(3ADEV\) 	timings->sharing = SAMSUNG_SHARING;
73d275c40cSAlbert ARIBAUD \(3ADEV\) 	timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
74d275c40cSAlbert ARIBAUD \(3ADEV\) 	timings->ctrla = SAMSUNG_V_ACTIMA_165;
75d275c40cSAlbert ARIBAUD \(3ADEV\) 	timings->ctrlb = SAMSUNG_V_ACTIMB_165;
76d275c40cSAlbert ARIBAUD \(3ADEV\) 	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
77d275c40cSAlbert ARIBAUD \(3ADEV\) 	timings->mr = SAMSUNG_V_MR_165;
78d275c40cSAlbert ARIBAUD \(3ADEV\) }
79d275c40cSAlbert ARIBAUD \(3ADEV\) #endif
80d275c40cSAlbert ARIBAUD \(3ADEV\) 
81d275c40cSAlbert ARIBAUD \(3ADEV\) static const struct ns16550_platdata cairo_serial = {
822f6ed3b8SAdam Ford 	.base = OMAP34XX_UART2,
832f6ed3b8SAdam Ford 	.reg_shift = 2,
8417fa0326SHeiko Schocher 	.clock = V_NS16550_CLK,
8517fa0326SHeiko Schocher 	.fcr = UART_FCR_DEFVAL,
86d275c40cSAlbert ARIBAUD \(3ADEV\) };
87d275c40cSAlbert ARIBAUD \(3ADEV\) 
88d275c40cSAlbert ARIBAUD \(3ADEV\) U_BOOT_DEVICE(cairo_uart) = {
89c7b9686dSThomas Chou 	"ns16550_serial",
90d275c40cSAlbert ARIBAUD \(3ADEV\) 	&cairo_serial
91d275c40cSAlbert ARIBAUD \(3ADEV\) };
92d275c40cSAlbert ARIBAUD \(3ADEV\) 
93d275c40cSAlbert ARIBAUD \(3ADEV\) /* force SPL booting into U-Boot, not Linux */
94d275c40cSAlbert ARIBAUD \(3ADEV\) #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)95d275c40cSAlbert ARIBAUD \(3ADEV\) int spl_start_uboot(void)
96d275c40cSAlbert ARIBAUD \(3ADEV\) {
97d275c40cSAlbert ARIBAUD \(3ADEV\) 	return 1;
98d275c40cSAlbert ARIBAUD \(3ADEV\) }
99d275c40cSAlbert ARIBAUD \(3ADEV\) #endif
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