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Searched refs:t1 (Results 1 – 25 of 37) sorted by relevance

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/rk3399_rockchip-uboot/board/pb1x00/
H A Dlowlevel_init.S28 li t1, 0x00000083
29 sw t1, 0(t0)
32 li t1, 0x33030A10
33 sw t1, 0(t0)
36 li t1, 0x11803E40
37 sw t1, 0(t0)
40 li t1, 0xBE00000C
41 lw t2, 0(t1)
43 sw t2, 0(t1)
46 li t1, 0xBE000014
[all …]
/rk3399_rockchip-uboot/board/dbau1x00/
H A Dlowlevel_init.S28 li t1, 0x00000040
29 sw t1, 0(t0)
32 li t1, 0x22080a20
33 sw t1, 0(t0)
36 li t1, 0x10c03f00
37 sw t1, 0(t0)
40 li t1, 0x00000080
41 sw t1, 0(t0)
44 li t1, 0x22080a20
45 sw t1, 0(t0)
[all …]
/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar933x/
H A Dlowlevel_init.S83 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
84 ori t1, t1, 0x0800
85 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
87 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
89 and t1, t1, t2
90 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
102 andi t1, t5, 0x10
103 bnez t1, 2b
106 li t1, 0x02110E
107 sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
[all …]
/rk3399_rockchip-uboot/board/imgtec/malta/
H A Dlowlevel_init.S39 li t1, MALTA_REVISION_CORID_CORE_LV
40 beq t0, t1, _gt64120
43 li t1, MALTA_REVISION_CORID_CORE_FPGA6
44 beq t0, t1, _msc01
66 PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE)
68 sw t0, GT_ISD_OFS(t1)
71 PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE)
75 sw t0, GT_PCI0IOLD_OFS(t1)
77 sw t0, GT_PCI0IOHD_OFS(t1)
81 sw t0, GT_PCI0M0LD_OFS(t1)
[all …]
/rk3399_rockchip-uboot/arch/mips/mach-ath79/qca953x/
H A Dlowlevel_init.S103 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
105 or t1, t1, t2
106 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
108 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
110 and t1, t1, t2
111 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
116 li t1, 0x01
117 sw t1, QCA953X_RTC_REG_SYNC_RESET(t0)
123 lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
124 andi t1, t1, 0x02
[all …]
/rk3399_rockchip-uboot/arch/mips/lib/
H A Dcache_init.S153 lw t1, GCR_L2_CONFIG(t0)
154 bgez t1, l2_probe_done
156 ext R_L2_LINE, t1, \
162 ext t2, t1, GCR_L2_CONFIG_ASSOC_SHIFT, GCR_L2_CONFIG_ASSOC_BITS
166 ext t2, t1, GCR_L2_CONFIG_SETSZ_SHIFT, GCR_L2_CONFIG_SETSZ_BITS
172 or t1, t1, GCR_L2_CONFIG_BYPASS
173 sw t1, GCR_L2_CONFIG(t0)
201 li t1, 2
202 sllv R_L2_LINE, t1, R_L2_LINE
204 srl t1, t0, MIPS_CONF2_SA_SHF
[all …]
/rk3399_rockchip-uboot/board/qemu-mips/
H A Dlowlevel_init.S18 li t1, 0x00400000
19 mtc0 t1, CP0_STATUS
25 li t1, 0x00000003
26 mtc0 t1, CP0_CONFIG
32 li t1, 0x00800000
33 mtc0 t1, CP0_CAUSE
/rk3399_rockchip-uboot/board/imgtec/boston/
H A Dlowlevel_init.S30 1: lw t1, 0(t0)
31 andi t1, t1, BOSTON_PLAT_DDR3STAT_CALIB
32 beqz t1, 1b
/rk3399_rockchip-uboot/arch/mips/cpu/
H A Dcm_init.S32 PTR_LI t1, CONFIG_MIPS_CM_BASE
33 beq t0, t1, 2f
39 sw t1, GCR_BASE(t0)
H A Dstart.S41 mtc0 t1, CP0_WATCHHI,\sel
57 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
58 and sp, t1, t0 # force 16 byte alignment
75 blt t0, t1, 1b
193 li t1, 0x7 # Clear I, R and W conditions
/rk3399_rockchip-uboot/arch/mips/mach-pic32/
H A Dlowlevel_init.S18 li t1, 0x00800000
19 mtc0 t1, CP0_CAUSE
/rk3399_rockchip-uboot/drivers/video/
H A Dmb862xx.c235 unsigned long t1, hsync, vsync; in card_init() local
286 t1 = (res_mode->left_margin + res_mode->xres + in card_init()
288 t1 *= 8; in card_init()
289 t1 *= res_mode->pixclock; in card_init()
290 t1 /= 1000; in card_init()
291 hsync = 1000000000L / t1; in card_init()
292 t1 *= (res_mode->upper_margin + res_mode->yres + in card_init()
294 t1 /= 1000; in card_init()
295 vsync = 1000000000L / t1; in card_init()
H A Dati_radeon_fb.c623 unsigned long t1, hsynch, vsynch; in video_hw_init() local
670 t1 = (res_mode->left_margin + res_mode->xres + in video_hw_init()
672 t1 *= 8; in video_hw_init()
673 t1 *= res_mode->pixclock; in video_hw_init()
674 t1 /= 1000; in video_hw_init()
675 hsynch = 1000000000L / t1; in video_hw_init()
676 t1 *= (res_mode->upper_margin + res_mode->yres + in video_hw_init()
678 t1 /= 1000; in video_hw_init()
679 vsynch = 1000000000L / t1; in video_hw_init()
H A Dmx3fb.c810 unsigned long t1, hsynch, vsynch; in video_hw_init() local
850 t1 = (mode->left_margin + mode->xres + in video_hw_init()
852 t1 *= 8; in video_hw_init()
853 t1 *= mode->pixclock; in video_hw_init()
854 t1 /= 1000; in video_hw_init()
855 hsynch = 1000000000L / t1; in video_hw_init()
856 t1 *= (mode->upper_margin + mode->yres + in video_hw_init()
858 t1 /= 1000; in video_hw_init()
859 vsynch = 1000000000L / t1; in video_hw_init()
/rk3399_rockchip-uboot/arch/powerpc/lib/
H A D_ashldi3.S37 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
39 or r3,r3,r6 # MSW |= t1
H A D_lshrdi3.S37 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
39 or r4,r4,r6 # LSW |= t1
H A D_ashrdi3.S37 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
40 or r4,r4,r6 # LSW |= t1
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A Dsha256_ce_core.S23 t1 .req v23
35 add t1.4s, v\s0\().4s, \rc\().4s
42 sha256h dg0q, dg1q, t1.4s
43 sha256h2 dg1q, dg2q, t1.4s
H A Dsha1_ce_core.S23 t1 .req v5
39 add t1.4s, v\s0\().4s, \rc\().4s
51 sha1\op dg0q, dg2s, t1.4s
/rk3399_rockchip-uboot/arch/mips/include/asm/
H A Dregdef.h29 #define t1 $9 macro
80 #define t1 $13 macro
/rk3399_rockchip-uboot/lib/avb/libavb/
H A Davb_sha512.c88 t1 = wv[h] + SHA512_F2(wv[e]) + CH(wv[e], wv[f], wv[g]) + sha512_k[j] + \
91 wv[d] += t1; \
92 wv[h] = t1 + t2; \
174 uint64_t t1, t2; in SHA512_transform() local
316 t1 = wv[7] + SHA512_F2(wv[4]) + CH(wv[4], wv[5], wv[6]) + sha512_k[j] + in SHA512_transform()
322 wv[4] = wv[3] + t1; in SHA512_transform()
326 wv[0] = t1 + t2; in SHA512_transform()
H A Davb_sha256.c103 t1 = wv[h] + SHA256_F2(wv[e]) + CH(wv[e], wv[f], wv[g]) + sha256_k[j] + \
106 wv[d] += t1; \
107 wv[h] = t1 + t2; \
159 uint32_t t1, t2; in SHA256_transform() local
184 t1 = wv[7] + SHA256_F2(wv[4]) + CH(wv[4], wv[5], wv[6]) + sha256_k[j] + in SHA256_transform()
190 wv[4] = wv[3] + t1; in SHA256_transform()
194 wv[0] = t1 + t2; in SHA256_transform()
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx5/
H A Dclock.c554 u64 pd, mfi = 1, mfn, mfd, t1; in calc_pll_params() local
583 t1 = n_target * pd; in calc_pll_params()
584 do_div(t1, (4 * n_ref)); in calc_pll_params()
585 mfi = t1; in calc_pll_params()
597 t1 = n_target * pd; in calc_pll_params()
598 do_div(t1, 4); in calc_pll_params()
599 t1 -= n_ref * mfi; in calc_pll_params()
600 t1 *= mfd; in calc_pll_params()
601 do_div(t1, n_ref); in calc_pll_params()
602 mfn = t1; in calc_pll_params()
/rk3399_rockchip-uboot/drivers/thermal/
H A Dimx_thermal.c58 int t1, n1; in read_cpu_temperature() local
70 t1 = 25; /* t1 always 25C */ in read_cpu_temperature()
95 c2 = n1 * c1 + 1000000 * t1; in read_cpu_temperature()
/rk3399_rockchip-uboot/arch/nds32/cpu/n1213/
H A Dstart.S354 ! $t1= bit width of I cache line size(ISZ)
355 addi $t1, $p0, 2
358 sll $t5, $t4, $t1 ! get $t5 cache line size
364 add $t3, $t2, $t1 ! SHIFT
389 ! $t1= bit width of D cache line size(DSZ)
390 addi $t1, $p0, 2
393 sll $t5, $t4, $t1 ! get $t5 cache line size
399 add $t3, $t2, $t1 ! SHIFT

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