| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | grf_rk3576.h | 37 uint32_t soc_con[6]; /* address offset: 0x0000 */ member
40 check_member(rk3576_center_grf_reg, soc_con, 0x0000);
216 uint32_t soc_con[7]; /* address offset: 0x0000 */ member
229 uint32_t soc_con[3]; /* address offset: 0x0000 */ member
239 uint32_t soc_con[8]; /* address offset: 0x0000 */ member
263 uint32_t soc_con[18]; /* address offset: 0x0000 */ member
266 check_member(rk3576_pmu1_sgrf_reg, soc_con, 0x0000);
287 uint32_t soc_con[13]; /* address offset: 0x0000 */ member
314 uint32_t soc_con[21]; /* address offset: 0x0020 */ member
379 uint32_t soc_con[34]; /* address offset: 0x0000 */ member
[all …]
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| H A D | grf_rk322x.h | 45 unsigned int soc_con[7]; member
87 unsigned int soc_con[11]; member
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| H A D | grf_rk3562.h | 14 uint32_t soc_con[13]; /* address offset: 0x0100 */ member
37 uint32_t soc_con[7]; /* address offset: 0x0400 */ member
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| H A D | grf_px30.h | 92 unsigned int soc_con[6]; member
133 unsigned int soc_con[3]; member
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| H A D | grf_rk3328.h | 86 u32 soc_con[11]; member
121 u32 soc_con[6]; member
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| H A D | grf_rk3528.h | 28 uint32_t soc_con[8]; /* Address Offset: 0x70000 */ member
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| H A D | grf_rk1808.h | 177 unsigned int soc_con[5]; member
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| H A D | grf_rv1126.h | 231 unsigned int soc_con[7]; member
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| H A D | grf_rv1108.h | 137 u32 soc_con[4]; member
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk322x/ |
| H A D | rk322x.c | 32 rk_setreg(&grf->soc_con[2], 1 << 0); in arch_cpu_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3328/ |
| H A D | rk3328.c | 62 rk_setreg(&grf->soc_con[4], 1 << 12); in arch_cpu_init()
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 368 writel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]); in phy_softreset()
374 writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]); in phy_softreset()
387 writel(GRF_MSCH_NOC_16BIT_EN, &grf->soc_con[0]); in set_bw()
394 &grf->soc_con[0]); in set_bw()
436 writel(bw | GRF_DDR3_EN, &grf->soc_con[0]); in pctl_cfg()
463 writel(bw | GRF_LPDDR2_3_EN, &grf->soc_con[0]); in pctl_cfg()
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| H A D | sdram_rv1108.c | 33 rk_clrsetreg(&priv->pmu_grf->soc_con[0], in enable_ddr_io_ret()
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| H A D | sdram_rv1126.c | 3440 &dram->pmugrf->soc_con[0]); in ddr_set_rate()
3473 &dram->pmugrf->soc_con[0]); in ddr_set_rate()
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| /rk3399_rockchip-uboot/drivers/net/ |
| H A D | gmac_rockchip.c | 669 rk_clrsetreg(&grf->soc_con[0], in rk3562_set_gmac_speed()
683 rk_clrsetreg(&grf->soc_con[0], in rk3562_set_gmac_speed()
705 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_RMII_DIV_MASK, div); in rk3562_set_gmac_speed()
707 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_RGMII_DIV_MASK, div); in rk3562_set_gmac_speed()
1555 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RMII_MODE_MASK, mode); in rk3562_set_to_rmii()
1594 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RGMII_MODE_MASK, in rk3562_set_to_rgmii()
2315 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_SELET_MASK, val); in rk3562_set_clock_selection()
2326 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_SELET_MASK, val); in rk3562_set_clock_selection()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rv1126/ |
| H A D | rv1126.c | 393 rk_clrsetreg(&pmugrf->soc_con[6], UART1_IO_SEL_MASK, in board_debug_uart_init()
403 rk_clrsetreg(&pmugrf->soc_con[6], UART1_IO_SEL_MASK, in board_debug_uart_init()
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 256 readl(&grf->soc_con[4]) & BIT(14)) { in rk3328_gmac2io_set_clk()
1033 rk_clrreg(&grf->soc_con[4], BIT(14)); in rk3328_gmac2io_ext_set_parent()
1049 rk_setreg(&grf->soc_con[4], BIT(14)); in rk3328_gmac2io_ext_set_parent()
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