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/rk3399_rockchip-uboot/arch/arm/dts/
H A Drv1126-dram-default-timing.dtsi82 * CA de-skew, one step is 20ps, range 0-63
83 * name rule: ddr4(pad_name)_ddr3_lpddr3_lpddr4_de-skew
85 a0_a3_a3_cke1-a_de-skew = <7>;
86 a1_ba1_null_cke0-b_de-skew = <7>;
87 a2_a9_a9_a4-a_de-skew = <7>;
88 a3_a15_null_a5-b_de-skew = <7>;
89 a4_a6_a6_ck-a_de-skew = <7>;
90 a5_a12_null_odt0-b_de-skew = <7>;
91 a6_ba2_null_a0-a_de-skew = <7>;
92 a7_a4_a4_odt0-a_de-skew = <7>;
[all …]
H A Dsama5d3xcm.dtsi47 txen-skew-ps = <800>;
48 txc-skew-ps = <3000>;
49 rxdv-skew-ps = <400>;
50 rxc-skew-ps = <3000>;
51 rxd0-skew-ps = <400>;
52 rxd1-skew-ps = <400>;
53 rxd2-skew-ps = <400>;
54 rxd3-skew-ps = <400>;
61 txen-skew-ps = <800>;
62 txc-skew-ps = <3000>;
[all …]
H A Dsama5d3xcm_cmp.dtsi46 txen-skew-ps = <800>;
47 txc-skew-ps = <3000>;
48 rxdv-skew-ps = <400>;
49 rxc-skew-ps = <3000>;
50 rxd0-skew-ps = <400>;
51 rxd1-skew-ps = <400>;
52 rxd2-skew-ps = <400>;
53 rxd3-skew-ps = <400>;
60 txen-skew-ps = <800>;
61 txc-skew-ps = <3000>;
[all …]
H A Dsocfpga_cyclone5_de1_soc.dts37 rxd0-skew-ps = <420>;
38 rxd1-skew-ps = <420>;
39 rxd2-skew-ps = <420>;
40 rxd3-skew-ps = <420>;
41 txen-skew-ps = <0>;
42 txc-skew-ps = <1860>;
43 rxdv-skew-ps = <420>;
44 rxc-skew-ps = <1680>;
H A Dsocfpga_cyclone5_de0_nano_soc.dts37 rxd0-skew-ps = <420>;
38 rxd1-skew-ps = <420>;
39 rxd2-skew-ps = <420>;
40 rxd3-skew-ps = <420>;
41 txen-skew-ps = <0>;
42 txc-skew-ps = <1860>;
43 rxdv-skew-ps = <420>;
44 rxc-skew-ps = <1680>;
H A Dsocfpga_cyclone5_de10_nano.dts39 rxd0-skew-ps = <420>;
40 rxd1-skew-ps = <420>;
41 rxd2-skew-ps = <420>;
42 rxd3-skew-ps = <420>;
43 txen-skew-ps = <0>;
44 txc-skew-ps = <1860>;
45 rxdv-skew-ps = <420>;
46 rxc-skew-ps = <1680>;
H A Dsocfpga_cyclone5_sockit.dts37 rxd0-skew-ps = <0>;
38 rxd1-skew-ps = <0>;
39 rxd2-skew-ps = <0>;
40 rxd3-skew-ps = <0>;
41 txen-skew-ps = <0>;
42 txc-skew-ps = <2600>;
43 rxdv-skew-ps = <0>;
44 rxc-skew-ps = <2000>;
H A Dsocfpga_cyclone5_socrates.dts41 rxd0-skew-ps = <0>;
42 rxd1-skew-ps = <0>;
43 rxd2-skew-ps = <0>;
44 rxd3-skew-ps = <0>;
45 txen-skew-ps = <0>;
46 txc-skew-ps = <2600>;
47 rxdv-skew-ps = <0>;
48 rxc-skew-ps = <2000>;
H A Dsocfpga_arria5_socdk.dts47 rxd0-skew-ps = <0>;
48 rxd1-skew-ps = <0>;
49 rxd2-skew-ps = <0>;
50 rxd3-skew-ps = <0>;
51 txen-skew-ps = <0>;
52 txc-skew-ps = <2600>;
53 rxdv-skew-ps = <0>;
54 rxc-skew-ps = <2000>;
H A Dsocfpga_cyclone5_is1.dts44 rxd0-skew-ps = <0>;
45 rxd1-skew-ps = <0>;
46 rxd2-skew-ps = <0>;
47 rxd3-skew-ps = <0>;
48 txen-skew-ps = <0>;
49 txc-skew-ps = <2600>;
50 rxdv-skew-ps = <0>;
51 rxc-skew-ps = <2000>;
H A Dsocfpga_cyclone5_socdk.dts47 rxd0-skew-ps = <0>;
48 rxd1-skew-ps = <0>;
49 rxd2-skew-ps = <0>;
50 rxd3-skew-ps = <0>;
51 txen-skew-ps = <0>;
52 txc-skew-ps = <2600>;
53 rxdv-skew-ps = <0>;
54 rxc-skew-ps = <2000>;
H A Dsocfpga_cyclone5_vining_fpga.dts37 rxd0-skew-ps = <0>;
38 rxd1-skew-ps = <0>;
39 rxd2-skew-ps = <0>;
40 rxd3-skew-ps = <0>;
41 txen-skew-ps = <0>;
42 txc-skew-ps = <2600>;
43 rxdv-skew-ps = <0>;
44 rxc-skew-ps = <2000>;
H A Dimx6qdl-icore-rqs.dtsi60 rxc-skew-ps = <1140>;
61 txc-skew-ps = <1140>;
62 txen-skew-ps = <600>;
63 rxdv-skew-ps = <240>;
64 rxd0-skew-ps = <420>;
65 rxd1-skew-ps = <600>;
66 rxd2-skew-ps = <420>;
67 rxd3-skew-ps = <240>;
68 txd0-skew-ps = <60>;
69 txd1-skew-ps = <60>;
[all …]
/rk3399_rockchip-uboot/doc/device-tree-bindings/net/
H A Dmicrel-ksz90x1.txt13 All skew control options are specified in picoseconds. The minimum
19 - rxc-skew-ps : Skew control of RXC pad
20 - rxdv-skew-ps : Skew control of RX CTL pad
21 - txc-skew-ps : Skew control of TXC pad
22 - txen-skew-ps : Skew control of TX CTL pad
23 - rxd0-skew-ps : Skew control of RX data 0 pad
24 - rxd1-skew-ps : Skew control of RX data 1 pad
25 - rxd2-skew-ps : Skew control of RX data 2 pad
26 - rxd3-skew-ps : Skew control of RX data 3 pad
27 - txd0-skew-ps : Skew control of TX data 0 pad
[all …]
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_phy_px30.c171 struct ddr_phy_regs *phy_regs, struct ddr_phy_skew *skew, in phy_cfg() argument
200 &skew->a0_a1_skew[0], 15 * 4); in phy_cfg()
202 &skew->cs0_dm0_skew[0], 44 * 4); in phy_cfg()
204 &skew->cs1_dm0_skew[0], 44 * 4); in phy_cfg()
H A Dsdram-rk3308-ddr-skew.inc17 {/*cmd,addr de-skew*/
H A Dsdram_px30.c61 struct ddr_phy_skew skew = { variable
432 phy_cfg(dram->phy, &sdram_params->phy_regs, sdram_params->skew, in sdram_init_()
640 sdram_configs[0].skew = &skew; in get_default_sdram_config()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_phy_px30.h58 struct ddr_phy_regs *phy_regs, struct ddr_phy_skew *skew,
H A Dsdram_px30.h210 struct ddr_phy_skew *skew; member
/rk3399_rockchip-uboot/board/Seagate/nas220/
H A Dkwbimage.cfg117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
118 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/Marvell/guruplug/
H A Dkwbimage.cfg113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
114 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/Seagate/dockstar/
H A Dkwbimage.cfg116 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
117 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/Synology/ds109/
H A Dkwbimage.cfg117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
118 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/Marvell/dreamplug/
H A Dkwbimage.cfg114 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
115 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/Seagate/goflexhome/
H A Dkwbimage.cfg119 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
120 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh

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