1*6bd041f0SDalon Westergreen/* 2*6bd041f0SDalon Westergreen * Copyright (C) 2017, Intel Corporation 3*6bd041f0SDalon Westergreen * 4*6bd041f0SDalon Westergreen * based on socfpga_cyclone5_de0_nano_soc.dts 5*6bd041f0SDalon Westergreen * 6*6bd041f0SDalon Westergreen * SPDX-License-Identifier: GPL-2.0+ 7*6bd041f0SDalon Westergreen */ 8*6bd041f0SDalon Westergreen 9*6bd041f0SDalon Westergreen#include "socfpga_cyclone5.dtsi" 10*6bd041f0SDalon Westergreen 11*6bd041f0SDalon Westergreen/ { 12*6bd041f0SDalon Westergreen model = "Terasic DE10-Nano"; 13*6bd041f0SDalon Westergreen compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 14*6bd041f0SDalon Westergreen 15*6bd041f0SDalon Westergreen chosen { 16*6bd041f0SDalon Westergreen bootargs = "console=ttyS0,115200"; 17*6bd041f0SDalon Westergreen }; 18*6bd041f0SDalon Westergreen 19*6bd041f0SDalon Westergreen aliases { 20*6bd041f0SDalon Westergreen ethernet0 = &gmac1; 21*6bd041f0SDalon Westergreen udc0 = &usb1; 22*6bd041f0SDalon Westergreen }; 23*6bd041f0SDalon Westergreen 24*6bd041f0SDalon Westergreen memory { 25*6bd041f0SDalon Westergreen name = "memory"; 26*6bd041f0SDalon Westergreen device_type = "memory"; 27*6bd041f0SDalon Westergreen reg = <0x0 0x40000000>; /* 1GB */ 28*6bd041f0SDalon Westergreen }; 29*6bd041f0SDalon Westergreen 30*6bd041f0SDalon Westergreen soc { 31*6bd041f0SDalon Westergreen u-boot,dm-pre-reloc; 32*6bd041f0SDalon Westergreen }; 33*6bd041f0SDalon Westergreen}; 34*6bd041f0SDalon Westergreen 35*6bd041f0SDalon Westergreen&gmac1 { 36*6bd041f0SDalon Westergreen status = "okay"; 37*6bd041f0SDalon Westergreen phy-mode = "rgmii"; 38*6bd041f0SDalon Westergreen 39*6bd041f0SDalon Westergreen rxd0-skew-ps = <420>; 40*6bd041f0SDalon Westergreen rxd1-skew-ps = <420>; 41*6bd041f0SDalon Westergreen rxd2-skew-ps = <420>; 42*6bd041f0SDalon Westergreen rxd3-skew-ps = <420>; 43*6bd041f0SDalon Westergreen txen-skew-ps = <0>; 44*6bd041f0SDalon Westergreen txc-skew-ps = <1860>; 45*6bd041f0SDalon Westergreen rxdv-skew-ps = <420>; 46*6bd041f0SDalon Westergreen rxc-skew-ps = <1680>; 47*6bd041f0SDalon Westergreen}; 48*6bd041f0SDalon Westergreen 49*6bd041f0SDalon Westergreen&gpio0 { 50*6bd041f0SDalon Westergreen status = "okay"; 51*6bd041f0SDalon Westergreen}; 52*6bd041f0SDalon Westergreen 53*6bd041f0SDalon Westergreen&gpio1 { 54*6bd041f0SDalon Westergreen status = "okay"; 55*6bd041f0SDalon Westergreen}; 56*6bd041f0SDalon Westergreen 57*6bd041f0SDalon Westergreen&gpio2 { 58*6bd041f0SDalon Westergreen status = "okay"; 59*6bd041f0SDalon Westergreen}; 60*6bd041f0SDalon Westergreen 61*6bd041f0SDalon Westergreen&mmc0 { 62*6bd041f0SDalon Westergreen status = "okay"; 63*6bd041f0SDalon Westergreen u-boot,dm-pre-reloc; 64*6bd041f0SDalon Westergreen}; 65*6bd041f0SDalon Westergreen 66*6bd041f0SDalon Westergreen&usb1 { 67*6bd041f0SDalon Westergreen status = "okay"; 68*6bd041f0SDalon Westergreen}; 69