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/rk3399_rockchip-uboot/doc/device-tree-bindings/reset/
H A Dreset.txt8 Hardware blocks typically receive a reset signal. This signal is generated by
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
20 A word on where to place reset signal consumers in device tree: It is possible
21 in hardware for a reset signal to affect multiple logically separate HW blocks
22 at once. In this case, it would be unwise to represent this reset signal in
26 children of the bus are affected by the reset signal, or an individual HW
29 rather than to slavishly enumerate the reset signal that affects each HW
49 for each reset signal that affects the device, or that the
55 reset-names: List of reset signal name strings sorted in the same order as
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/rk3399_rockchip-uboot/doc/device-tree-bindings/serial/
H A Dsnps-dw-apb-uart.txt27 - dcd-override : Override the DCD modem status signal. This signal will always
30 - dsr-override : Override the DTS modem status signal. This signal will always
33 - cts-override : Override the CTS modem status signal. This signal will always
36 - ri-override : Override the RI modem status signal. This signal will always be
/rk3399_rockchip-uboot/test/py/
H A Du_boot_spawn.py10 import signal
57 signal.signal(signal.SIGHUP, signal.SIG_DFL)
/rk3399_rockchip-uboot/test/py/tests/
H A Dtest_sandbox_exit.py7 import signal
21 u_boot_console.kill(signal.SIGINT)
/rk3399_rockchip-uboot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg141 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
142 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
143 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
144 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
149 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
150 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
151 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
152 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
H A Dkwbimage-lsxhl.cfg141 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
142 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
143 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
144 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
149 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
150 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
151 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
152 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
/rk3399_rockchip-uboot/doc/device-tree-bindings/gpio/
H A Dgpio.txt78 defined by the binding for the device. If the board inverts the signal between
80 opposite physical level than the signal at the device's pin.
82 When the device's signal polarity is configurable, the binding for the
85 a) Define a single static polarity for the signal, with the expectation that
87 that signal polarity.
99 concepts of configurable signal polarity in the device, and possible board-
100 level signal inversion.
104 b) Pick a single option for device signal polarity, and document this choice
105 in the binding. The gpio-specifier should represent the polarity of the signal
107 particular signal polarity choice. If software chooses to program the device
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/rk3399_rockchip-uboot/board/d-link/dns325/
H A Dkwbimage.cfg130 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
131 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
132 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
133 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
137 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
138 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
139 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
140 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
/rk3399_rockchip-uboot/arch/powerpc/include/asm/
H A Dsigcontext.h9 int signal; member
/rk3399_rockchip-uboot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt25 The EQOS transmit path clock. The HW signal name is clk_tx_i.
30 The EQOS receive path clock. The HW signal name is clk_rx_i.
41 APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
45 separate clock for the master and slave bus interfaces. The HW signal name
48 The PTP reference clock. The HW signal name is clk_ptp_ref_i.
85 - interrupts: Should contain the core's combined interrupt signal
91 - "eqos". The reset to the entire module. The HW signal name is hreset_n
H A Dstmmac.txt34 - resets: Should contain a phandle to the STMMAC reset signal, if any
35 - reset-names: Should contain the reset signal name "stmmaceth", if a
/rk3399_rockchip-uboot/doc/
H A DREADME.imx520 This option should be enabled for boards having a SYS_ON_OFF_CTL signal
21 connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
H A DREADME.video59 - hpd_delay=<int> - How long to wait for the hdmi HPD signal in milliseconds
61 time for the monitor to assert the HPD signal. This configures how long to
62 wait for the HPD signal before assuming no cable is connected.
H A DREADME.LED40 CONFIG_STATUS_LED_RED is the red LED. It is used to signal errors. This must be
H A DREADME.arm-relocation159 Program received signal SIGSTOP, Stopped (signal).
/rk3399_rockchip-uboot/drivers/pwm/
H A DKconfig6 control over the duty cycle (high and low time) of the signal. This
10 time that the signal is high.
/rk3399_rockchip-uboot/doc/device-tree-bindings/leds/
H A Dleds-bcm6328.txt24 - brcm,serial-clk-low : Boolean, makes clock signal active low.
26 - brcm,serial-dat-low : Boolean, makes data signal active low.
H A Dleds-bcm6358.txt16 - brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8.
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dmeson-gxbb-odroidc2.dts91 * signal name from schematics: TFLASH_VDD_EN
111 * signal name from schematics: TF_3V3N_1V8_EN
240 * WARNING: The USB Hub on the Odroid-C2 needs a reset signal
242 * This signal should be handled by a USB specific power sequence
/rk3399_rockchip-uboot/doc/device-tree-bindings/video/
H A Drockchip-lvds.txt17 serialized LVDS signal.
H A Ddisplay-timing.txt46 for displays. If a display supports multiple signal timings, the native-mode
/rk3399_rockchip-uboot/drivers/reset/
H A DKconfig8 modules are equipped with a reset signal, typically driven by some
20 modules are equipped with a reset signal, typically driven by some
/rk3399_rockchip-uboot/common/
H A Dcli_hush.c1699 signal(SIGINT, SIG_DFL);
1700 signal(SIGQUIT, SIG_DFL);
1701 signal(SIGTERM, SIG_DFL);
1702 signal(SIGTSTP, SIG_DFL);
1703 signal(SIGTTIN, SIG_DFL);
1704 signal(SIGTTOU, SIG_DFL);
1705 signal(SIGCHLD, SIG_DFL);
3369 signal(SIGINT, SIG_IGN);
3370 signal(SIGQUIT, SIG_IGN);
3371 signal(SIGTERM, SIG_IGN);
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/rk3399_rockchip-uboot/doc/device-tree-bindings/pci/
H A Darmada8k-pcie.txt22 card reset signal release.
/rk3399_rockchip-uboot/doc/device-tree-bindings/pwm/
H A Dpwm.txt48 - PWM_POLARITY_INVERTED: invert the PWM signal polarity

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