xref: /rk3399_rockchip-uboot/doc/device-tree-bindings/gpio/gpio.txt (revision 25cd3b965f2349f1f7ab9cb92b18aaab81d9a827)
19f4cd020SSimon GlassSpecifying GPIO information for devices
29f4cd020SSimon Glass============================================
39f4cd020SSimon Glass
49f4cd020SSimon Glass1) gpios property
59f4cd020SSimon Glass-----------------
69f4cd020SSimon Glass
79f4cd020SSimon GlassNodes that makes use of GPIOs should specify them using one or more
89f4cd020SSimon Glassproperties, each containing a 'gpio-list':
99f4cd020SSimon Glass
109f4cd020SSimon Glass	gpio-list ::= <single-gpio> [gpio-list]
119f4cd020SSimon Glass	single-gpio ::= <gpio-phandle> <gpio-specifier>
129f4cd020SSimon Glass	gpio-phandle : phandle to gpio controller node
139f4cd020SSimon Glass	gpio-specifier : Array of #gpio-cells specifying specific gpio
149f4cd020SSimon Glass			 (controller specific)
159f4cd020SSimon Glass
169f4cd020SSimon GlassGPIO properties should be named "[<name>-]gpios", with <name> being the purpose
179f4cd020SSimon Glassof this GPIO for the device. While a non-existent <name> is considered valid
189f4cd020SSimon Glassfor compatibility reasons (resolving to the "gpios" property), it is not allowed
199f4cd020SSimon Glassfor new bindings.
209f4cd020SSimon Glass
219f4cd020SSimon GlassGPIO properties can contain one or more GPIO phandles, but only in exceptional
229f4cd020SSimon Glasscases should they contain more than one. If your device uses several GPIOs with
239f4cd020SSimon Glassdistinct functions, reference each of them under its own property, giving it a
249f4cd020SSimon Glassmeaningful name. The only case where an array of GPIOs is accepted is when
259f4cd020SSimon Glassseveral GPIOs serve the same function (e.g. a parallel data line).
269f4cd020SSimon Glass
279f4cd020SSimon GlassThe exact purpose of each gpios property must be documented in the device tree
289f4cd020SSimon Glassbinding of the device.
299f4cd020SSimon Glass
309f4cd020SSimon GlassThe following example could be used to describe GPIO pins used as device enable
319f4cd020SSimon Glassand bit-banged data signals:
329f4cd020SSimon Glass
339f4cd020SSimon Glass	gpio1: gpio1 {
349f4cd020SSimon Glass		gpio-controller
359f4cd020SSimon Glass		 #gpio-cells = <2>;
369f4cd020SSimon Glass	};
379f4cd020SSimon Glass	gpio2: gpio2 {
389f4cd020SSimon Glass		gpio-controller
399f4cd020SSimon Glass		 #gpio-cells = <1>;
409f4cd020SSimon Glass	};
419f4cd020SSimon Glass	[...]
429f4cd020SSimon Glass
439f4cd020SSimon Glass	enable-gpios = <&gpio2 2>;
449f4cd020SSimon Glass	data-gpios = <&gpio1 12 0>,
459f4cd020SSimon Glass		     <&gpio1 13 0>,
469f4cd020SSimon Glass		     <&gpio1 14 0>,
479f4cd020SSimon Glass		     <&gpio1 15 0>;
489f4cd020SSimon Glass
499f4cd020SSimon GlassNote that gpio-specifier length is controller dependent.  In the
509f4cd020SSimon Glassabove example, &gpio1 uses 2 cells to specify a gpio, while &gpio2
519f4cd020SSimon Glassonly uses one.
529f4cd020SSimon Glass
539f4cd020SSimon Glassgpio-specifier may encode: bank, pin position inside the bank,
549f4cd020SSimon Glasswhether pin is open-drain and whether pin is logically inverted.
559f4cd020SSimon GlassExact meaning of each specifier cell is controller specific, and must
569f4cd020SSimon Glassbe documented in the device tree binding for the device. Use the macros
579f4cd020SSimon Glassdefined in include/dt-bindings/gpio/gpio.h whenever possible:
589f4cd020SSimon Glass
599f4cd020SSimon GlassExample of a node using GPIOs:
609f4cd020SSimon Glass
619f4cd020SSimon Glass	node {
629f4cd020SSimon Glass		enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>;
639f4cd020SSimon Glass	};
649f4cd020SSimon Glass
659f4cd020SSimon GlassGPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes
669f4cd020SSimon GlassGPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
679f4cd020SSimon Glass
689f4cd020SSimon Glass1.1) GPIO specifier best practices
699f4cd020SSimon Glass----------------------------------
709f4cd020SSimon Glass
719f4cd020SSimon GlassA gpio-specifier should contain a flag indicating the GPIO polarity; active-
72ba257793SMasahiro Yamadahigh or active-low. If it does, the following best practices should be
73ba257793SMasahiro Yamadafollowed:
749f4cd020SSimon Glass
759f4cd020SSimon GlassThe gpio-specifier's polarity flag should represent the physical level at the
769f4cd020SSimon GlassGPIO controller that achieves (or represents, for inputs) a logically asserted
779f4cd020SSimon Glassvalue at the device. The exact definition of logically asserted should be
789f4cd020SSimon Glassdefined by the binding for the device. If the board inverts the signal between
799f4cd020SSimon Glassthe GPIO controller and the device, then the gpio-specifier will represent the
809f4cd020SSimon Glassopposite physical level than the signal at the device's pin.
819f4cd020SSimon Glass
829f4cd020SSimon GlassWhen the device's signal polarity is configurable, the binding for the
839f4cd020SSimon Glassdevice must either:
849f4cd020SSimon Glass
859f4cd020SSimon Glassa) Define a single static polarity for the signal, with the expectation that
869f4cd020SSimon Glassany software using that binding would statically program the device to use
879f4cd020SSimon Glassthat signal polarity.
889f4cd020SSimon Glass
899f4cd020SSimon GlassThe static choice of polarity may be either:
909f4cd020SSimon Glass
919f4cd020SSimon Glassa1) (Preferred) Dictated by a binding-specific DT property.
929f4cd020SSimon Glass
939f4cd020SSimon Glassor:
949f4cd020SSimon Glass
959f4cd020SSimon Glassa2) Defined statically by the DT binding itself.
969f4cd020SSimon Glass
979f4cd020SSimon GlassIn particular, the polarity cannot be derived from the gpio-specifier, since
989f4cd020SSimon Glassthat would prevent the DT from separately representing the two orthogonal
999f4cd020SSimon Glassconcepts of configurable signal polarity in the device, and possible board-
1009f4cd020SSimon Glasslevel signal inversion.
1019f4cd020SSimon Glass
1029f4cd020SSimon Glassor:
1039f4cd020SSimon Glass
1049f4cd020SSimon Glassb) Pick a single option for device signal polarity, and document this choice
1059f4cd020SSimon Glassin the binding. The gpio-specifier should represent the polarity of the signal
1069f4cd020SSimon Glass(at the GPIO controller) assuming that the device is configured for this
1079f4cd020SSimon Glassparticular signal polarity choice. If software chooses to program the device
1089f4cd020SSimon Glassto generate or receive a signal of the opposite polarity, software will be
1099f4cd020SSimon Glassresponsible for correctly interpreting (inverting) the GPIO signal at the GPIO
1109f4cd020SSimon Glasscontroller.
1119f4cd020SSimon Glass
1129f4cd020SSimon Glass2) gpio-controller nodes
1139f4cd020SSimon Glass------------------------
1149f4cd020SSimon Glass
1159f4cd020SSimon GlassEvery GPIO controller node must contain both an empty "gpio-controller"
1169f4cd020SSimon Glassproperty, and a #gpio-cells integer property, which indicates the number of
1179f4cd020SSimon Glasscells in a gpio-specifier.
1189f4cd020SSimon Glass
1199f4cd020SSimon GlassExample of two SOC GPIO banks defined as gpio-controller nodes:
1209f4cd020SSimon Glass
1219f4cd020SSimon Glass	qe_pio_a: gpio-controller@1400 {
1229f4cd020SSimon Glass		compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
1239f4cd020SSimon Glass		reg = <0x1400 0x18>;
1249f4cd020SSimon Glass		gpio-controller;
1259f4cd020SSimon Glass		#gpio-cells = <2>;
1269f4cd020SSimon Glass	};
1279f4cd020SSimon Glass
1289f4cd020SSimon Glass	qe_pio_e: gpio-controller@1460 {
1299f4cd020SSimon Glass		compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
1309f4cd020SSimon Glass		reg = <0x1460 0x18>;
1319f4cd020SSimon Glass		gpio-controller;
1329f4cd020SSimon Glass		#gpio-cells = <2>;
1339f4cd020SSimon Glass	};
1349f4cd020SSimon Glass
1359f4cd020SSimon Glass2.1) gpio- and pin-controller interaction
1369f4cd020SSimon Glass-----------------------------------------
1379f4cd020SSimon Glass
1389f4cd020SSimon GlassSome or all of the GPIOs provided by a GPIO controller may be routed to pins
1399f4cd020SSimon Glasson the package via a pin controller. This allows muxing those pins between
1409f4cd020SSimon GlassGPIO and other functions.
1419f4cd020SSimon Glass
1429f4cd020SSimon GlassIt is useful to represent which GPIOs correspond to which pins on which pin
1439f4cd020SSimon Glasscontrollers. The gpio-ranges property described below represents this, and
1449f4cd020SSimon Glasscontains information structures as follows:
1459f4cd020SSimon Glass
1469f4cd020SSimon Glass	gpio-range-list ::= <single-gpio-range> [gpio-range-list]
1479f4cd020SSimon Glass	single-gpio-range ::= <numeric-gpio-range> | <named-gpio-range>
1489f4cd020SSimon Glass	numeric-gpio-range ::=
1499f4cd020SSimon Glass			<pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
1509f4cd020SSimon Glass	named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
151ba257793SMasahiro Yamada	pinctrl-phandle : phandle to pin controller node
1529f4cd020SSimon Glass	gpio-base : Base GPIO ID in the GPIO controller
1539f4cd020SSimon Glass	pinctrl-base : Base pinctrl pin ID in the pin controller
1549f4cd020SSimon Glass	count : The number of GPIOs/pins in this range
1559f4cd020SSimon Glass
1569f4cd020SSimon GlassThe "pin controller node" mentioned above must conform to the bindings
1579f4cd020SSimon Glassdescribed in ../pinctrl/pinctrl-bindings.txt.
1589f4cd020SSimon Glass
1599f4cd020SSimon GlassIn case named gpio ranges are used (ranges with both <pinctrl-base> and
1609f4cd020SSimon Glass<count> set to 0), the property gpio-ranges-group-names contains one string
1619f4cd020SSimon Glassfor every single-gpio-range in gpio-ranges:
1629f4cd020SSimon Glass	gpiorange-names-list ::= <gpiorange-name> [gpiorange-names-list]
1639f4cd020SSimon Glass	gpiorange-name : Name of the pingroup associated to the GPIO range in
1649f4cd020SSimon Glass			the respective pin controller.
1659f4cd020SSimon Glass
1669f4cd020SSimon GlassElements of gpiorange-names-list corresponding to numeric ranges contain
1679f4cd020SSimon Glassthe empty string. Elements of gpiorange-names-list corresponding to named
1689f4cd020SSimon Glassranges contain the name of a pin group defined in the respective pin
1699f4cd020SSimon Glasscontroller. The number of pins/GPIOs in the range is the number of pins in
1709f4cd020SSimon Glassthat pin group.
1719f4cd020SSimon Glass
1729f4cd020SSimon GlassPrevious versions of this binding required all pin controller nodes that
1739f4cd020SSimon Glasswere referenced by any gpio-ranges property to contain a property named
1749f4cd020SSimon Glass#gpio-range-cells with value <3>. This requirement is now deprecated.
1759f4cd020SSimon GlassHowever, that property may still exist in older device trees for
1769f4cd020SSimon Glasscompatibility reasons, and would still be required even in new device
1779f4cd020SSimon Glasstrees that need to be compatible with older software.
1789f4cd020SSimon Glass
1799f4cd020SSimon GlassExample 1:
1809f4cd020SSimon Glass
1819f4cd020SSimon Glass	qe_pio_e: gpio-controller@1460 {
1829f4cd020SSimon Glass		#gpio-cells = <2>;
1839f4cd020SSimon Glass		compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
1849f4cd020SSimon Glass		reg = <0x1460 0x18>;
1859f4cd020SSimon Glass		gpio-controller;
1869f4cd020SSimon Glass		gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
1879f4cd020SSimon Glass	};
1889f4cd020SSimon Glass
1899f4cd020SSimon GlassHere, a single GPIO controller has GPIOs 0..9 routed to pin controller
1909f4cd020SSimon Glasspinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's
1919f4cd020SSimon Glasspins 50..59.
1929f4cd020SSimon Glass
1939f4cd020SSimon GlassExample 2:
1949f4cd020SSimon Glass
1959f4cd020SSimon Glass	gpio_pio_i: gpio-controller@14B0 {
1969f4cd020SSimon Glass		#gpio-cells = <2>;
1979f4cd020SSimon Glass		compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
1989f4cd020SSimon Glass		reg = <0x1480 0x18>;
1999f4cd020SSimon Glass		gpio-controller;
2009f4cd020SSimon Glass		gpio-ranges =			<&pinctrl1 0 20 10>,
2019f4cd020SSimon Glass						<&pinctrl2 10 0 0>,
2029f4cd020SSimon Glass						<&pinctrl1 15 0 10>,
2039f4cd020SSimon Glass						<&pinctrl2 25 0 0>;
2049f4cd020SSimon Glass		gpio-ranges-group-names =	"",
2059f4cd020SSimon Glass						"foo",
2069f4cd020SSimon Glass						"",
2079f4cd020SSimon Glass						"bar";
2089f4cd020SSimon Glass	};
2099f4cd020SSimon Glass
2109f4cd020SSimon GlassHere, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO
2119f4cd020SSimon Glassranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2
2129f4cd020SSimon Glassare named "foo" and "bar".
2137e044b9aSHeiko Schocher
2147e044b9aSHeiko Schocher3) GPIO hog definitions
2157e044b9aSHeiko Schocher-----------------------
2167e044b9aSHeiko Schocher
2177e044b9aSHeiko SchocherThe GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
2187e044b9aSHeiko Schocherproviding automatic GPIO request and configuration as part of the
2197e044b9aSHeiko Schochergpio-controller's driver probe function.
2207e044b9aSHeiko Schocher
2217e044b9aSHeiko SchocherEach GPIO hog definition is represented as a child node of the GPIO controller.
2227e044b9aSHeiko SchocherRequired properties:
2237e044b9aSHeiko Schocher- gpio-hog:   A property specifying that this child node represents a GPIO hog.
2247e044b9aSHeiko Schocher- gpios:      Store the GPIO information (id, flags) for the GPIO to
2257e044b9aSHeiko Schocher	      affect.
2267e044b9aSHeiko Schocher
2277e044b9aSHeiko Schocher              ! Not yet support more than one gpio !
2287e044b9aSHeiko Schocher
2297e044b9aSHeiko SchocherOnly one of the following properties scanned in the order shown below.
2307e044b9aSHeiko Schocher- input:      A property specifying to set the GPIO direction as input.
2317e044b9aSHeiko Schocher- output-low  A property specifying to set the GPIO direction as output with
2327e044b9aSHeiko Schocher	      the value low.
2337e044b9aSHeiko Schocher- output-high A property specifying to set the GPIO direction as output with
2347e044b9aSHeiko Schocher	      the value high.
2357e044b9aSHeiko Schocher
2367e044b9aSHeiko SchocherOptional properties:
2377e044b9aSHeiko Schocher- line-name:  The GPIO label name. If not present the node name is used.
2387e044b9aSHeiko Schocher
2397e044b9aSHeiko SchocherExample:
2407e044b9aSHeiko Schocher
2417e044b9aSHeiko Schocher        tca6416@20 {
2427e044b9aSHeiko Schocher                compatible = "ti,tca6416";
2437e044b9aSHeiko Schocher                reg = <0x20>;
2447e044b9aSHeiko Schocher                #gpio-cells = <2>;
2457e044b9aSHeiko Schocher                gpio-controller;
2467e044b9aSHeiko Schocher
2477e044b9aSHeiko Schocher                env_reset {
2487e044b9aSHeiko Schocher                        gpio-hog;
2497e044b9aSHeiko Schocher                        input;
2507e044b9aSHeiko Schocher                        gpios = <6 GPIO_ACTIVE_LOW>;
2517e044b9aSHeiko Schocher                };
2527e044b9aSHeiko Schocher                boot_rescue {
2537e044b9aSHeiko Schocher                        gpio-hog;
2547e044b9aSHeiko Schocher                        input;
255*25cd3b96SHeiko Schocher                        line-name = "foo-bar-gpio";
2567e044b9aSHeiko Schocher                        gpios = <7 GPIO_ACTIVE_LOW>;
2577e044b9aSHeiko Schocher                };
2587e044b9aSHeiko Schocher        };
2597e044b9aSHeiko Schocher
2607e044b9aSHeiko SchocherFor the above Example you can than access the gpio in your boardcode
2617e044b9aSHeiko Schocherwith:
2627e044b9aSHeiko Schocher
263*25cd3b96SHeiko Schocher	struct gpio_desc *desc;
264*25cd3b96SHeiko Schocher	int ret;
265*25cd3b96SHeiko Schocher
266*25cd3b96SHeiko Schocher	ret = gpio_hog_lookup_name("boot_rescue", &desc);
267*25cd3b96SHeiko Schocher	if (ret)
268*25cd3b96SHeiko Schocher		return;
269*25cd3b96SHeiko Schocher	if (dm_gpio_get_value(desc) == 1)
2707e044b9aSHeiko Schocher		printf("\nBooting into Rescue System\n");
271*25cd3b96SHeiko Schocher	else if (dm_gpio_get_value(desc) == 0)
2727e044b9aSHeiko Schocher		printf("\nBoot normal\n");
273