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Searched refs:shift (Results 1 – 25 of 209) sorted by relevance

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/rk3399_rockchip-uboot/include/
H A Dbitfield.h43 static inline uint bitfield_mask(uint shift, uint width) in bitfield_mask() argument
45 return ((1 << width) - 1) << shift; in bitfield_mask()
49 static inline uint bitfield_extract(uint reg_val, uint shift, uint width) in bitfield_extract() argument
51 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract()
58 static inline uint bitfield_replace(uint reg_val, uint shift, uint width, in bitfield_replace() argument
61 uint mask = bitfield_mask(shift, width); in bitfield_replace()
63 return (reg_val & ~mask) | ((bitfield_val << shift) & mask); in bitfield_replace()
75 uint shift = bitfield_shift(mask); in bitfield_extract_by_mask() local
77 return (reg_val & mask) >> shift; in bitfield_extract_by_mask()
87 uint shift = bitfield_shift(mask); in bitfield_replace_by_mask() local
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/bcu/
H A Dbcu-ld4.c18 int shift; in uniphier_ld4_bcu_init() local
27 shift = bd->dram_ch[0].size / 0x04000000 * 4; in uniphier_ld4_bcu_init()
28 writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ in uniphier_ld4_bcu_init()
30 shift -= 32; in uniphier_ld4_bcu_init()
31 writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ in uniphier_ld4_bcu_init()
33 shift -= 32; in uniphier_ld4_bcu_init()
34 writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ in uniphier_ld4_bcu_init()
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Drockchip_dmc.c536 u32 shift; in rk3328_de_skew_setting_2_register() local
545 shift = n % 2; in rk3328_de_skew_setting_2_register()
547 shift = (shift == 0) ? 4 : 0; in rk3328_de_skew_setting_2_register()
548 tim->ca_skew[offset] &= ~(0xf << shift); in rk3328_de_skew_setting_2_register()
549 tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift); in rk3328_de_skew_setting_2_register()
555 shift = ((n % 21) % 2); in rk3328_de_skew_setting_2_register()
557 shift = 0; in rk3328_de_skew_setting_2_register()
560 shift = (shift == 0) ? 4 : 0; in rk3328_de_skew_setting_2_register()
561 tim->cs0_skew[offset] &= ~(0xf << shift); in rk3328_de_skew_setting_2_register()
562 tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift); in rk3328_de_skew_setting_2_register()
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Domap3xxx-clocks.dtsi28 ti,bit-shift = <6>;
39 ti,bit-shift = <7>;
88 ti,bit-shift = <4>;
102 ti,bit-shift = <2>;
116 ti,bit-shift = <6>;
143 ti,bit-shift = <2>;
224 ti,bit-shift = <0x1b>;
248 ti,bit-shift = <16>;
266 ti,bit-shift = <0xc>;
295 ti,bit-shift = <27>;
[all …]
H A Ddra7xx-clocks.dtsi217 ti,autoidle-shift = <8>;
237 ti,autoidle-shift = <8>;
248 ti,autoidle-shift = <8>;
258 ti,bit-shift = <23>;
280 ti,autoidle-shift = <8>;
306 ti,autoidle-shift = <8>;
332 ti,bit-shift = <23>;
348 ti,autoidle-shift = <8>;
366 ti,bit-shift = <23>;
382 ti,autoidle-shift = <8>;
[all …]
H A Domap34xx-omap36xx-clocks.dtsi23 ti,bit-shift = <3>;
32 ti,bit-shift = <2>;
40 ti,bit-shift = <1>;
48 ti,bit-shift = <0>;
55 ti,bit-shift = <0>;
65 ti,bit-shift = <0>;
73 ti,bit-shift = <1>;
89 ti,bit-shift = <4>;
97 ti,bit-shift = <29>;
105 ti,bit-shift = <26>;
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi50 ti,bit-shift = <1>;
112 ti,bit-shift = <0>;
120 ti,bit-shift = <0>;
128 ti,bit-shift = <1>;
136 ti,bit-shift = <2>;
144 ti,bit-shift = <2>;
152 ti,bit-shift = <30>;
160 ti,bit-shift = <30>;
167 ti,bit-shift = <0>;
177 ti,bit-shift = <0>;
[all …]
H A Dam43xx-clocks.dtsi15 ti,bit-shift = <31>;
23 ti,bit-shift = <29>;
31 ti,bit-shift = <22>;
111 ti,bit-shift = <0>;
119 ti,bit-shift = <1>;
127 ti,bit-shift = <2>;
135 ti,bit-shift = <4>;
143 ti,bit-shift = <5>;
151 ti,bit-shift = <6>;
216 ti,autoidle-shift = <8>;
[all …]
H A Dam33xx-clocks.dtsi15 ti,bit-shift = <22>;
103 ti,bit-shift = <0>;
111 ti,bit-shift = <1>;
119 ti,bit-shift = <2>;
299 ti,bit-shift = <1>;
323 ti,bit-shift = <1>;
346 ti,bit-shift = <1>;
403 ti,bit-shift = <8>;
419 ti,bit-shift = <1>;
504 ti,bit-shift = <18>;
[all …]
H A Domap36xx-clocks.dtsi22 ti,bit-shift = <0x1e>;
32 ti,bit-shift = <0x1b>;
41 ti,bit-shift = <0xc>;
50 ti,bit-shift = <0x1c>;
59 ti,bit-shift = <0x1f>;
69 ti,bit-shift = <18>;
H A Domap36xx-omap3430es2plus-clocks.dtsi15 ti,bit-shift = <0>;
23 ti,bit-shift = <8>;
47 ti,bit-shift = <4>;
63 ti,bit-shift = <0>;
70 ti,bit-shift = <9>;
150 ti,bit-shift = <3>;
166 ti,bit-shift = <9>;
/rk3399_rockchip-uboot/drivers/misc/
H A Dpca9551_led.c43 u8 shift, buf; in pca9551_led_get_state() local
50 shift = led << 1; in pca9551_led_get_state()
53 shift = (led - 4) << 1; in pca9551_led_get_state()
60 *state = (buf >> shift) & 0x03; in pca9551_led_get_state()
67 u8 shift, buf, mask; in pca9551_led_set_state() local
74 shift = led << 1; in pca9551_led_set_state()
77 shift = (led - 4) << 1; in pca9551_led_set_state()
79 mask = 0x03 << shift; in pca9551_led_set_state()
85 buf = (buf & ~mask) | ((state & 0x03) << shift); in pca9551_led_set_state()
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c58 u32 shift, mask; in scg_sircdiv_get_rate() local
63 shift = SCG_SIRCDIV_DIV1_SHIFT; in scg_sircdiv_get_rate()
67 shift = SCG_SIRCDIV_DIV2_SHIFT; in scg_sircdiv_get_rate()
71 shift = SCG_SIRCDIV_DIV3_SHIFT; in scg_sircdiv_get_rate()
82 val = (reg & mask) >> shift; in scg_sircdiv_get_rate()
96 u32 shift, mask; in scg_fircdiv_get_rate() local
101 shift = SCG_FIRCDIV_DIV1_SHIFT; in scg_fircdiv_get_rate()
105 shift = SCG_FIRCDIV_DIV2_SHIFT; in scg_fircdiv_get_rate()
109 shift = SCG_FIRCDIV_DIV3_SHIFT; in scg_fircdiv_get_rate()
120 val = (reg & mask) >> shift; in scg_fircdiv_get_rate()
[all …]
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3528.c240 u32 div, mask, shift; in rk3528_ppll_matrix_get_rate() local
247 shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT; in rk3528_ppll_matrix_get_rate()
253 shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT; in rk3528_ppll_matrix_get_rate()
260 shift = CLK_MATRIX_125M_SRC_DIV_SHIFT; in rk3528_ppll_matrix_get_rate()
266 shift = CLK_MATRIX_25M_SRC_DIV_SHIFT; in rk3528_ppll_matrix_get_rate()
273 div = (readl(reg) & mask) >> shift; in rk3528_ppll_matrix_get_rate()
282 u32 id, div, mask, shift; in rk3528_ppll_matrix_set_rate() local
289 shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT; in rk3528_ppll_matrix_set_rate()
296 shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT; in rk3528_ppll_matrix_set_rate()
303 shift = CLK_MATRIX_125M_SRC_DIV_SHIFT; in rk3528_ppll_matrix_set_rate()
[all …]
/rk3399_rockchip-uboot/include/linux/
H A Dmath64.h150 static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift) in mul_u64_u32_shr() argument
152 return (u64)(((unsigned __int128)a * mul) >> shift); in mul_u64_u32_shr()
157 static inline u64 mul_u64_u64_shr(u64 a, u64 mul, unsigned int shift) in mul_u64_u64_shr() argument
159 return (u64)(((unsigned __int128)a * mul) >> shift); in mul_u64_u64_shr()
166 static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift) in mul_u64_u32_shr() argument
174 ret = mul_u32_u32(al, mul) >> shift; in mul_u64_u32_shr()
176 ret += mul_u32_u32(ah, mul) << (32 - shift); in mul_u64_u32_shr()
183 static inline u64 mul_u64_u64_shr(u64 a, u64 b, unsigned int shift) in mul_u64_u64_shr() argument
218 if (shift == 0) in mul_u64_u64_shr()
220 if (shift < 64) in mul_u64_u64_shr()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-kirkwood/
H A Dmpp.c56 int shift; in kirkwood_mpp_conf() local
69 shift = (num & 7) << 2; in kirkwood_mpp_conf()
72 sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf; in kirkwood_mpp_conf()
77 mpp_ctrl[num / 8] &= ~(0xf << shift); in kirkwood_mpp_conf()
78 mpp_ctrl[num / 8] |= sel << shift; in kirkwood_mpp_conf()
/rk3399_rockchip-uboot/drivers/qe/
H A Duccf.c39 u8 *reg_num, u8 *shift) in ucc_get_cmxucr_reg() argument
45 *shift = 16; in ucc_get_cmxucr_reg()
50 *shift = 0; in ucc_get_cmxucr_reg()
55 *shift = 16; in ucc_get_cmxucr_reg()
60 *shift = 0; in ucc_get_cmxucr_reg()
65 *shift = 16; in ucc_get_cmxucr_reg()
70 *shift = 0; in ucc_get_cmxucr_reg()
75 *shift = 16; in ucc_get_cmxucr_reg()
80 *shift = 0; in ucc_get_cmxucr_reg()
91 u8 shift = 0; in ucc_set_clk_src() local
[all …]
/rk3399_rockchip-uboot/drivers/bios_emulator/x86emu/
H A Dops2.c358 u8 shift; in x86emuOp2_shld_IMM() local
372 shift = fetch_byte_imm(); in x86emuOp2_shld_IMM()
373 DECODE_PRINTF2("%d\n", shift); in x86emuOp2_shld_IMM()
376 destval = shld_long(destval,*shiftreg,shift); in x86emuOp2_shld_IMM()
385 shift = fetch_byte_imm(); in x86emuOp2_shld_IMM()
386 DECODE_PRINTF2("%d\n", shift); in x86emuOp2_shld_IMM()
389 destval = shld_word(destval,*shiftreg,shift); in x86emuOp2_shld_IMM()
400 shift = fetch_byte_imm(); in x86emuOp2_shld_IMM()
401 DECODE_PRINTF2("%d\n", shift); in x86emuOp2_shld_IMM()
403 *destreg = shld_long(*destreg,*shiftreg,shift); in x86emuOp2_shld_IMM()
[all …]
/rk3399_rockchip-uboot/drivers/i2c/
H A Dsoft_i2c.c332 int shift; in soft_i2c_read() local
367 shift = (alen-1) * 8; in soft_i2c_read()
369 if(write_byte(addr >> shift)) { in soft_i2c_read()
373 shift -= 8; in soft_i2c_read()
407 int shift, failures = 0; in soft_i2c_write() local
418 shift = (alen-1) * 8; in soft_i2c_write()
420 if(write_byte(addr >> shift)) { in soft_i2c_write()
424 shift -= 8; in soft_i2c_write()
/rk3399_rockchip-uboot/arch/arm/mach-stm32/stm32f4/
H A Dclock.c193 u32 shift = 0; in clock_get() local
218 shift = ahb_psc_table[( in clock_get()
221 return sysclk >>= shift; in clock_get()
224 shift = apb_psc_table[( in clock_get()
227 return sysclk >>= shift; in clock_get()
230 shift = apb_psc_table[( in clock_get()
233 return sysclk >>= shift; in clock_get()
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/
H A Dsoc-info.c15 unsigned int shift) in __uniphier_get_revision_field() argument
19 return (revision >> shift) & mask; in __uniphier_get_revision_field()
/rk3399_rockchip-uboot/drivers/video/drm/
H A Drockchip_vop.h26 #define __REG_SET(x, off, mask, shift, v, write_mask) \ argument
27 vop_mask_write(x, off, mask, shift, v, write_mask)
32 __REG_SET(vop, off + reg.offset, mask, reg.shift, \
173 static inline uint16_t scl_cal_scale(int src, int dst, int shift) in scl_cal_scale() argument
175 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); in scl_cal_scale()
244 uint32_t shift:5; member
534 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; in vop_read_reg()
538 uint32_t mask, uint32_t shift, uint32_t v, in vop_mask_write() argument
545 v = ((v & mask) << shift) | (mask << (shift + 16)); in vop_mask_write()
549 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); in vop_mask_write()
[all …]
/rk3399_rockchip-uboot/arch/mips/lib/
H A Dreloc.c46 unsigned int shift = 0; in read_uint() local
51 val |= (new & 0x7f) << shift; in read_uint()
52 shift += 7; in read_uint()
/rk3399_rockchip-uboot/drivers/led/
H A Dled_bcm6328.c46 uint8_t shift; member
52 return ((readl_be(priv->mode) >> priv->shift) & LED_MODE_MASK); in bcm6328_led_get_mode()
57 clrsetbits_be32(priv->mode, (LED_MODE_MASK << priv->shift), in bcm6328_led_set_mode()
58 (mode << priv->shift)); in bcm6328_led_set_mode()
202 priv->shift = (pin << 1); in bcm6328_led_probe()
206 priv->shift = ((pin - 8) << 1); in bcm6328_led_probe()
/rk3399_rockchip-uboot/include/zfs/
H A Dspa.h31 #define BF32_GET_SB(x, low, len, shift, bias) \ argument
32 ((BF32_GET(x, low, len) + (bias)) << (shift))
33 #define BF64_GET_SB(x, low, len, shift, bias) \ argument
34 ((BF64_GET(x, low, len) + (bias)) << (shift))
36 #define BF32_SET_SB(x, low, len, shift, bias, val) \ argument
37 BF32_SET(x, low, len, ((val) >> (shift)) - (bias))
38 #define BF64_SET_SB(x, low, len, shift, bias, val) \ argument
39 BF64_SET(x, low, len, ((val) >> (shift)) - (bias))

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