240 	u32 div, mask, shift;  in rk3528_ppll_matrix_get_rate()  local
247 		shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;  in rk3528_ppll_matrix_get_rate()
253 		shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;  in rk3528_ppll_matrix_get_rate()
260 		shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;  in rk3528_ppll_matrix_get_rate()
266 		shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;  in rk3528_ppll_matrix_get_rate()
273 	div = (readl(reg) & mask) >> shift;  in rk3528_ppll_matrix_get_rate()
282 	u32 id, div, mask, shift;  in rk3528_ppll_matrix_set_rate()  local
289 		shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;  in rk3528_ppll_matrix_set_rate()
296 		shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;  in rk3528_ppll_matrix_set_rate()
303 		shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;  in rk3528_ppll_matrix_set_rate()
308 		shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;  in rk3528_ppll_matrix_set_rate()
316 		rk_clrsetreg(&cru->pcieclksel_con[id], mask, (div - 1) << shift);  in rk3528_ppll_matrix_set_rate()
318 		rk_clrsetreg(&cru->clksel_con[id], mask, (div - 1) << shift);  in rk3528_ppll_matrix_set_rate()
327 	u32 sel, div, mask, shift, con;  in rk3528_cgpll_matrix_get_rate()  local
337 		shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_get_rate()
344 		shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_get_rate()
351 		shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_get_rate()
357 		shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_get_rate()
363 		shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_get_rate()
371 		shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_get_rate()
377 		shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_get_rate()
384 		shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_get_rate()
390 		shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_get_rate()
398 		shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_get_rate()
405 		shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;  in rk3528_cgpll_matrix_get_rate()
425 	div = (readl(&cru->clksel_con[con]) & mask) >> shift;  in rk3528_cgpll_matrix_get_rate()
435 	u32 sel, div, mask, shift, con;  in rk3528_cgpll_matrix_set_rate()  local
445 		shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_set_rate()
452 		shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_set_rate()
459 		shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_set_rate()
465 		shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_set_rate()
471 		shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_set_rate()
479 		shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_set_rate()
485 		shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_set_rate()
492 		shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_set_rate()
498 		shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_set_rate()
506 		shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;  in rk3528_cgpll_matrix_set_rate()
513 		shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;  in rk3528_cgpll_matrix_set_rate()
541 	rk_clrsetreg(&cru->clksel_con[con], mask, (div - 1) << shift);  in rk3528_cgpll_matrix_set_rate()
551 	u32 id, sel, con, mask, shift;  in rk3528_i2c_get_clk()  local
559 		shift = CLK_I2C0_SEL_SHIFT;  in rk3528_i2c_get_clk()
565 		shift = CLK_I2C1_SEL_SHIFT;  in rk3528_i2c_get_clk()
571 		shift = CLK_I2C2_SEL_SHIFT;  in rk3528_i2c_get_clk()
578 		shift = CLK_I2C3_SEL_SHIFT;  in rk3528_i2c_get_clk()
584 		shift = CLK_I2C4_SEL_SHIFT;  in rk3528_i2c_get_clk()
590 		shift = CLK_I2C5_SEL_SHIFT;  in rk3528_i2c_get_clk()
596 		shift = CLK_I2C6_SEL_SHIFT;  in rk3528_i2c_get_clk()
602 		shift = CLK_I2C7_SEL_SHIFT;  in rk3528_i2c_get_clk()
613 	sel = (con & mask) >> shift;  in rk3528_i2c_get_clk()
630 	u32 id, sel, mask, shift;  in rk3528_i2c_set_clk()  local
646 		shift = CLK_I2C0_SEL_SHIFT;  in rk3528_i2c_set_clk()
652 		shift = CLK_I2C1_SEL_SHIFT;  in rk3528_i2c_set_clk()
658 		shift = CLK_I2C2_SEL_SHIFT;  in rk3528_i2c_set_clk()
665 		shift = CLK_I2C3_SEL_SHIFT;  in rk3528_i2c_set_clk()
671 		shift = CLK_I2C4_SEL_SHIFT;  in rk3528_i2c_set_clk()
677 		shift = CLK_I2C5_SEL_SHIFT;  in rk3528_i2c_set_clk()
682 		shift = CLK_I2C6_SEL_SHIFT;  in rk3528_i2c_set_clk()
688 		shift = CLK_I2C7_SEL_SHIFT;  in rk3528_i2c_set_clk()
696 		rk_clrsetreg(&cru->pmuclksel_con[id], mask, sel << shift);  in rk3528_i2c_set_clk()
698 		rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);  in rk3528_i2c_set_clk()
706 	u32 id, sel, con, mask, shift;  in rk3528_spi_get_clk()  local
713 		shift = CLK_SPI0_SEL_SHIFT;  in rk3528_spi_get_clk()
719 		shift = CLK_SPI1_SEL_SHIFT;  in rk3528_spi_get_clk()
726 	sel = (con & mask) >> shift;  in rk3528_spi_get_clk()
743 	u32 id, sel, mask, shift;  in rk3528_spi_set_clk()  local
758 		shift = CLK_SPI0_SEL_SHIFT;  in rk3528_spi_set_clk()
764 		shift = CLK_SPI1_SEL_SHIFT;  in rk3528_spi_set_clk()
770 	rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);  in rk3528_spi_set_clk()
778 	u32 id, sel, con, mask, shift;  in rk3528_pwm_get_clk()  local
785 		shift = CLK_PWM0_SEL_SHIFT;  in rk3528_pwm_get_clk()
791 		shift = CLK_PWM1_SEL_SHIFT;  in rk3528_pwm_get_clk()
799 	sel = (con & mask) >> shift;  in rk3528_pwm_get_clk()
814 	u32 id, sel, mask, shift;  in rk3528_pwm_set_clk()  local
827 		shift = CLK_PWM0_SEL_SHIFT;  in rk3528_pwm_set_clk()
833 		shift = CLK_PWM1_SEL_SHIFT;  in rk3528_pwm_set_clk()
840 	rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);  in rk3528_pwm_set_clk()
878 	u32 div, mask, shift;  in rk3528_adc_set_clk()  local
883 		shift =	CLK_SARADC_DIV_SHIFT;  in rk3528_adc_set_clk()
888 		shift =	CLK_TSADC_TSEN_DIV_SHIFT;  in rk3528_adc_set_clk()
893 		shift =	CLK_TSADC_DIV_SHIFT;  in rk3528_adc_set_clk()
901 	rk_clrsetreg(&cru->clksel_con[74], mask, (div - 1) << shift);  in rk3528_adc_set_clk()
2074 	u32 id, sel, con, mask, shift;  in rk3528_crypto_get_rate()  local
2081 		shift = CLK_CORE_CRYPTO_SEL_SHIFT;  in rk3528_crypto_get_rate()
2087 		shift = CLK_PKA_CRYPTO_SEL_SHIFT;  in rk3528_crypto_get_rate()
2095 	sel = (con & mask) >> shift;  in rk3528_crypto_get_rate()
2112 	u32 id, sel, mask, shift;  in rk3528_crypto_set_rate()  local
2127 		shift = CLK_CORE_CRYPTO_SEL_SHIFT;  in rk3528_crypto_set_rate()
2133 		shift = CLK_PKA_CRYPTO_SEL_SHIFT;  in rk3528_crypto_set_rate()
2140 	rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);  in rk3528_crypto_set_rate()