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/rk3399_rockchip-uboot/doc/device-tree-bindings/video/
H A Dintel-gma.txt15 - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms)
18 - intel,panel-power-up-delay : T1+T2 time sequence
19 - intel,panel-power-down-delay : T3 time sequence
20 - intel,panel-power-backlight-on-delay : T5 time sequence
21 - intel,panel-power-backlight-off-delay : Tx time sequence
/rk3399_rockchip-uboot/tools/buildman/
H A Dtest.py109 sequence = 0
115 comm.sequence = sequence
116 sequence += 1
149 if ((boardnum >= 1 and boardnum >= commit.sequence) or
150 boardnum == 4 and commit.sequence == 6):
H A Dcontrol.py287 commits[commit].sequence = commit
/rk3399_rockchip-uboot/doc/
H A DI2C_Edge_Conditions25 The device will interpret this sequence as a WRITE command and
39 the I2C bus reset sequence.
H A DREADME.autoboot68 entered before the specified time the boot delay sequence is
130 sequence to be interrupted by ctrl-c, in addition to the
132 provides an escape sequence from the limited "password"
H A DREADME.splashprepare6 sequence. It gives the board an opportunity to prepare the splash
H A DREADME.cfi18 Some flash chips seem to have trouble with this reset sequence.
H A DREADME.arm-caches49 - The following sequence is advisable while disabling d-cache:
H A DREADME.SPL81 stack usage at various points in run sequence of SPL. The -fstack-usage option
H A DREADME.Heterogeneous-SoCs54 Though there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 -
H A DREADME.nios242 the sequence of these devices, like this,
/rk3399_rockchip-uboot/net/
H A Dping.c38 icmp->un.echo.sequence = htons(ping_seq_number++); in set_icmp_header()
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.lsch3157 command sequence. Below is one example for PBI commands for QDS which uses
283 more deployed during u-boot boot-sequence.
291 1. Command sequence for u-boot ethernet:
303 2. Command sequence for Linux boot:
319 3. Command sequence for AIOP boot:
H A DREADME.qspi18 command sequence for setting the boot location pointer. It's should point
/rk3399_rockchip-uboot/board/freescale/mpc8323erdb/
H A DREADME40 which is a shorter version of the manual sequence:
/rk3399_rockchip-uboot/doc/driver-model/
H A DREADME.txt324 The sequence to get a device to work is bind, ofdata_to_platdata (if using
473 to be locating by their 'sequence'. This numbering uniquely identifies a
475 the same sequence number.
481 where there are gaps in the sequence, this can lead to confusion and is
484 Each device can request a sequence number. If none is required then the
485 device will be automatically allocated the next available sequence number.
487 To specify the sequence number in the device tree an alias is typically
495 ("/serial@22230000") will be given sequence number 2. Any command or driver
511 Device sequence numbers are resolved when a device is probed. Before then
512 the sequence number is only a request which may or may not be honoured,
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drk3308-evb.dts142 panel-init-sequence = [
227 panel-exit-sequence = [
H A Dstm32f769-disco.dts63 /* Aliases for gpios so as to use sequence */
H A Dstm32f746-disco.dts68 /* Aliases for gpios so as to use sequence */
H A Drv1108-evb.dts118 panel-init-sequence = [
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
/rk3399_rockchip-uboot/doc/SPL/
H A DREADME.omap313 On these platforms the ROM supports trying a sequence of boot devices. Once
/rk3399_rockchip-uboot/board/freescale/p2041rdb/
H A DREADME90 The CPLD is used to control the power sequence and some serdes lane
/rk3399_rockchip-uboot/drivers/gpio/
H A DKconfig28 bool "Disable GPIO uclass sequence themselves with aliases"
32 Disable GPIO uclass sequence, this is a workaround when kernel
/rk3399_rockchip-uboot/doc/uImage.FIT/
H A Doverlay-fdt-boot.txt196 u-boot will retrieve the base blob and apply the overlays in sequence as

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