171e68402STom RiniOverview of SPL on OMAP3 devices 271e68402STom Rini================================ 371e68402STom Rini 471e68402STom RiniIntroduction 571e68402STom Rini------------ 671e68402STom Rini 771e68402STom RiniThis document provides an overview of how SPL functions on OMAP3 (and related 871e68402STom Rinisuch as am35x and am37x) processors. 971e68402STom Rini 1071e68402STom RiniMethodology 1171e68402STom Rini----------- 1271e68402STom Rini 1371e68402STom RiniOn these platforms the ROM supports trying a sequence of boot devices. Once 1471e68402STom Rinione has been used successfully to load SPL this information is stored in memory 1571e68402STom Riniand the location stored in a register. We will read this to determine where to 1671e68402STom Riniread U-Boot from in turn. 1771e68402STom Rini 1871e68402STom RiniMemory Map 1971e68402STom Rini---------- 2071e68402STom Rini 2171e68402STom RiniThis is an example of a typical setup. See top-level README for documentation 2271e68402STom Riniof which CONFIG variables control these values. For a given board and the 2371e68402STom Riniamount of DRAM available to it different values may need to be used. 2471e68402STom RiniNote that the size of the SPL text rodata and data is enforced with a CONFIG 2571e68402STom Rinioption and growing over that size results in a link error. The SPL stack 2671e68402STom Rinistarts at the top of SRAM (which is configurable) and grows downward. The 2771e68402STom Rinispace between the top of SRAM and the enforced upper bound on the size of the 2871e68402STom RiniSPL text, data and rodata is considered the safe stack area. Details on 2971e68402STom Riniconfirming this behavior are shown below. 3071e68402STom Rini 3171e68402STom RiniA portion of the system memory map looks as follows: 3271e68402STom RiniSRAM: 0x40200000 - 0x4020FFFF 3371e68402STom RiniDDR1: 0x80000000 - 0xBFFFFFFF 3471e68402STom Rini 3571e68402STom RiniOption 1 (SPL only): 3671e68402STom Rini0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata 37*e0820cccSTom Rini0x4020E000 - 0x4020FFFC: Area for the SPL stack. 3871e68402STom Rini0x80000000 - 0x8007FFFF: Area for the SPL BSS. 3971e68402STom Rini0x80100000: CONFIG_SYS_TEXT_BASE of U-Boot 4071e68402STom Rini0x80208000 - 0x80307FFF: malloc() pool available to SPL. 4171e68402STom Rini 4271e68402STom RiniOption 2 (SPL or X-Loader): 4371e68402STom Rini0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata 44*e0820cccSTom Rini0x4020E000 - 0x4020FFFC: Area for the SPL stack. 4571e68402STom Rini0x80008000: CONFIG_SYS_TEXT_BASE of U-Boot 4671e68402STom Rini0x87000000 - 0x8707FFFF: Area for the SPL BSS. 4771e68402STom Rini0x87080000 - 0x870FFFFF: malloc() pool available to SPL. 4871e68402STom Rini 4971e68402STom RiniFor the areas that reside within DDR1 they must not be used prior to s_init() 5071e68402STom Rinicompleting. Note that CONFIG_SYS_TEXT_BASE must be clear of the areas that SPL 5171e68402STom Riniuses while running. This is why we have two versions of the memory map that 5271e68402STom Rinionly vary in where the BSS and malloc pool reside. 53