1*83843c9bSAndre Przywara@ 2*83843c9bSAndre Przywara@ ARMv8 RMR reset sequence on Allwinner SoCs. 3*83843c9bSAndre Przywara@ 4*83843c9bSAndre Przywara@ All 64-bit capable Allwinner SoCs reset in AArch32 (and continue to 5*83843c9bSAndre Przywara@ exectute the Boot ROM in this state), so we need to switch to AArch64 6*83843c9bSAndre Przywara@ at some point. 7*83843c9bSAndre Przywara@ Section G6.2.133 of the ARMv8 ARM describes the Reset Management Register 8*83843c9bSAndre Przywara@ (RMR), which triggers a warm-reset of a core and can request to switch 9*83843c9bSAndre Przywara@ into a different execution state (AArch32 or AArch64). 10*83843c9bSAndre Przywara@ The address at which execution starts after the reset is held in the 11*83843c9bSAndre Przywara@ RVBAR system register, which is architecturally read-only. 12*83843c9bSAndre Przywara@ Allwinner provides a writable alias of this register in MMIO space, so 13*83843c9bSAndre Przywara@ we can easily set the start address of AArch64 code. 14*83843c9bSAndre Przywara@ This code below switches to AArch64 and starts execution at the specified 15*83843c9bSAndre Przywara@ start address. It needs to be assembled by an ARM(32) assembler and 16*83843c9bSAndre Przywara@ the machine code must be inserted as verbatim .word statements into the 17*83843c9bSAndre Przywara@ beginning of the AArch64 U-Boot code. 18*83843c9bSAndre Przywara@ To get the encoded bytes, use: 19*83843c9bSAndre Przywara@ ${CROSS_COMPILE}gcc -c -o rmr_switch.o rmr_switch.S 20*83843c9bSAndre Przywara@ ${CROSS_COMPILE}objdump -d rmr_switch.o 21*83843c9bSAndre Przywara@ 22*83843c9bSAndre Przywara@ The resulting words should be inserted into the U-Boot file at 23*83843c9bSAndre Przywara@ arch/arm/include/asm/arch-sunxi/boot0.h. 24*83843c9bSAndre Przywara@ 25*83843c9bSAndre Przywara@ This file is not build by the U-Boot build system, but provided only as a 26*83843c9bSAndre Przywara@ reference and to be able to regenerate a (probably fixed) version of this 27*83843c9bSAndre Przywara@ code found in encoded form in boot0.h. 28*83843c9bSAndre Przywara 29*83843c9bSAndre Przywara.text 30*83843c9bSAndre Przywara 31*83843c9bSAndre Przywara ldr r1, =0x017000a0 @ MMIO mapped RVBAR[0] register 32*83843c9bSAndre Przywara ldr r0, =0x57aA7add @ start address, to be replaced 33*83843c9bSAndre Przywara str r0, [r1] 34*83843c9bSAndre Przywara dsb sy 35*83843c9bSAndre Przywara isb sy 36*83843c9bSAndre Przywara mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register 37*83843c9bSAndre Przywara orr r0, r0, #3 @ request reset in AArch64 38*83843c9bSAndre Przywara mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register 39*83843c9bSAndre Przywara isb sy 40*83843c9bSAndre Przywara1: wfi 41*83843c9bSAndre Przywara b 1b 42