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Searched refs:sel_shift (Results 1 – 5 of 5) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3528.c328 u32 sel_mask = 0, sel_shift; in rk3528_cgpll_matrix_get_rate() local
365 sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT; in rk3528_cgpll_matrix_get_rate()
392 sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT; in rk3528_cgpll_matrix_get_rate()
413 sel = (readl(&cru->clksel_con[con]) & sel_mask) >> sel_shift; in rk3528_cgpll_matrix_get_rate()
436 u32 sel_mask = 0, sel_shift; in rk3528_cgpll_matrix_set_rate() local
473 sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT; in rk3528_cgpll_matrix_set_rate()
500 sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT; in rk3528_cgpll_matrix_set_rate()
543 rk_clrsetreg(&cru->clksel_con[con], sel_mask, sel << sel_shift); in rk3528_cgpll_matrix_set_rate()
1052 u32 sel_mask, sel_shift; in rk3528_dclk_vop_get_clk() local
1060 sel_shift = DCLK_VOP_SRC0_SEL_SHIFT; in rk3528_dclk_vop_get_clk()
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H A Dclk_rk3399.c671 uint8_t sel_shift; member
683 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
686 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
689 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
692 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
695 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
740 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)), in rk3399_spi_set_clk()
742 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); in rk3399_spi_set_clk()
H A Dclk_rk3368.c497 uint8_t sel_shift; member
504 [0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
505 [1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
506 [2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
556 (0x1 << spiclk->sel_shift)), in rk3368_spi_set_clk()
558 (1 << spiclk->sel_shift))); in rk3368_spi_set_clk()
H A Dclk_rk3576.c1178 u32 mask, div_shift, sel_shift; in rk3576_dclk_vop_set_clk() local
1188 sel_shift = DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_set_clk()
1197 sel_shift = DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_set_clk()
1206 sel_shift = DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_set_clk()
1219 DCLK_VOP_SRC_SEL_VPLL << sel_shift | in rk3576_dclk_vop_set_clk()
1227 DCLK_VOP_SRC_SEL_VPLL << sel_shift | in rk3576_dclk_vop_set_clk()
1273 best_sel << sel_shift | in rk3576_dclk_vop_set_clk()
1320 u32 mask, div_shift, sel_shift; in rk3576_clk_csihost_set_clk() local
1327 sel_shift = CLK_DSIHOST0_SEL_SHIFT; in rk3576_clk_csihost_set_clk()
1372 best_sel << sel_shift | in rk3576_clk_csihost_set_clk()
H A Dclk_rk3588.c1115 u32 mask, div_shift, sel_shift; in rk3588_dclk_vop_set_clk() local
1125 sel_shift = DCLK0_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_set_clk()
1134 sel_shift = DCLK1_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_set_clk()
1143 sel_shift = DCLK2_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_set_clk()
1151 sel_shift = DCLK3_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_set_clk()
1164 DCLK_VOP_SRC_SEL_V0PLL << sel_shift | in rk3588_dclk_vop_set_clk()
1172 DCLK_VOP_SRC_SEL_V0PLL << sel_shift | in rk3588_dclk_vop_set_clk()
1213 best_sel << sel_shift | in rk3588_dclk_vop_set_clk()