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Searched refs:rst (Results 1 – 25 of 51) sorted by relevance

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/rk3399_rockchip-uboot/drivers/reset/
H A Dreset-scmi.c13 static int scmi_reset_set_level(struct reset_ctl *rst, bool assert_not_deassert) in scmi_reset_set_level() argument
16 .domain_id = rst->id, in scmi_reset_set_level()
26 ret = devm_scmi_process_msg(rst->dev->parent, &msg); in scmi_reset_set_level()
33 static int scmi_reset_assert(struct reset_ctl *rst) in scmi_reset_assert() argument
35 return scmi_reset_set_level(rst, true); in scmi_reset_assert()
38 static int scmi_reset_deassert(struct reset_ctl *rst) in scmi_reset_deassert() argument
40 return scmi_reset_set_level(rst, false); in scmi_reset_deassert()
43 static int scmi_reset_request(struct reset_ctl *rst) in scmi_reset_request() argument
46 .domain_id = rst->id, in scmi_reset_request()
58 ret = devm_scmi_process_msg(rst->dev->parent, &msg); in scmi_reset_request()
[all …]
H A Dreset-bcm6345.c22 static int bcm6345_reset_assert(struct reset_ctl *rst) in bcm6345_reset_assert() argument
24 struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev); in bcm6345_reset_assert()
26 clrbits_be32(priv->regs, BIT(rst->id)); in bcm6345_reset_assert()
32 static int bcm6345_reset_deassert(struct reset_ctl *rst) in bcm6345_reset_deassert() argument
34 struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev); in bcm6345_reset_deassert()
36 setbits_be32(priv->regs, BIT(rst->id)); in bcm6345_reset_deassert()
42 static int bcm6345_reset_free(struct reset_ctl *rst) in bcm6345_reset_free() argument
47 static int bcm6345_reset_request(struct reset_ctl *rst) in bcm6345_reset_request() argument
49 if (rst->id >= MAX_RESETS) in bcm6345_reset_request()
52 return bcm6345_reset_assert(rst); in bcm6345_reset_request()
/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-inno-usb3.c255 static const char *get_rest_name(enum rockchip_u3phy_rest_req rst) in get_rest_name() argument
257 switch (rst) { in get_rest_name()
278 int rst; in rockchip_u3phy_rest_deassert() local
282 for (rst = PIPE_APB_RSTN; rst <= UTMI_APB_RSTN; rst++) { in rockchip_u3phy_rest_deassert()
283 if (u3phy->rsts[rst].dev) in rockchip_u3phy_rest_deassert()
284 reset_deassert(&u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
291 for (rst = U3_POR_RSTN; rst <= U2_POR_RSTN; rst++) { in rockchip_u3phy_rest_deassert()
292 if (u3phy->rsts[rst].dev) in rockchip_u3phy_rest_deassert()
293 reset_deassert(&u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
300 for (rst = PIPE_MAC_RSTN; rst <= UTMI_MAC_RSTN; rst++) in rockchip_u3phy_rest_deassert()
[all …]
/rk3399_rockchip-uboot/drivers/watchdog/
H A Drockchip_wdt.c27 struct reset_ctl rst; member
89 if (priv->rst.dev) in rockchip_wdt_start()
90 reset_deassert(&priv->rst); in rockchip_wdt_start()
104 if (priv->rst.dev) { in rockchip_wdt_stop()
105 reset_assert(&priv->rst); in rockchip_wdt_stop()
106 reset_deassert(&priv->rst); in rockchip_wdt_stop()
136 ret = reset_get_by_name(dev, "reset", &priv->rst); in rockchip_wdt_probe()
139 priv->rst.dev = NULL; in rockchip_wdt_probe()
/rk3399_rockchip-uboot/board/freescale/common/
H A Dqixis.c122 u8 rst; in board_assert_mem_reset() local
124 rst = QIXIS_READ(rst_frc[0]); in board_assert_mem_reset()
125 if (!(rst & QIXIS_RST_FORCE_MEM)) in board_assert_mem_reset()
126 QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM); in board_assert_mem_reset()
131 u8 rst; in board_deassert_mem_reset() local
133 rst = QIXIS_READ(rst_frc[0]); in board_deassert_mem_reset()
134 if (rst & QIXIS_RST_FORCE_MEM) in board_deassert_mem_reset()
135 QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM); in board_deassert_mem_reset()
H A Dpixis.h16 u8 rst; member
55 u8 rst; member
82 u8 rst; member
111 u8 rst; member
141 u8 rst; member
H A Dngpixis.c61 PIXIS_WRITE(rst, 0); in __pixis_reset()
128 printf("rst=%02x\n", PIXIS_READ(rst)); in pixis_dump_regs()
H A Dngpixis.h19 u8 rst; member
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/
H A Dopos6ul.c77 struct gpio_desc rst; in board_eth_init() local
93 ret = dm_gpio_lookup_name("GPIO4_2", &rst); in board_eth_init()
99 ret = dm_gpio_request(&rst, "phy-rst"); in board_eth_init()
105 dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT); in board_eth_init()
106 dm_gpio_set_value(&rst, 0); in board_eth_init()
108 dm_gpio_set_value(&rst, 1); in board_eth_init()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dcpu.c380 u32 rst, src = 2; in clock_enable_coresight() local
397 rst = CORESIGHT_UNLOCK; in clock_enable_coresight()
398 writel(rst, CSITE_CPU_DBG0_LAR); in clock_enable_coresight()
399 writel(rst, CSITE_CPU_DBG1_LAR); in clock_enable_coresight()
401 writel(rst, CSITE_CPU_DBG2_LAR); in clock_enable_coresight()
402 writel(rst, CSITE_CPU_DBG3_LAR); in clock_enable_coresight()
/rk3399_rockchip-uboot/doc/device-tree-bindings/reset/
H A Dreset.txt41 rst: reset-controller {
62 resets = <&rst 20>;
69 resets = <&rst 10> <&rst 11> <&rst 12> <&rst 11>;
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dmp.c46 struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); in wake_secondary_core_n() local
56 rst->brrl |= 1 << ((cluster * cluster_cores) + core); in wake_secondary_core_n()
72 struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); in fsl_layerscape_wake_seconday_cores() local
109 rst->brrl = cores; in fsl_layerscape_wake_seconday_cores()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dast2500-u-boot.dtsi15 rst: reset-controller { label
29 resets = <&rst AST_RESET_SDRAM>;
H A Dsocfpga_arria10.dtsi19 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
436 resets = <&rst EMAC0_RESET>;
455 resets = <&rst EMAC1_RESET>;
539 resets = <&rst FPGAMGR_RESET>;
743 rst: rstmgr@ffd05000 { label
745 compatible = "altr,rst-mgr";
833 resets = <&rst USB0_RESET>;
846 resets = <&rst USB1_RESET>;
H A Dstih407-family.dtsi404 reset-names = "miphy-sw-rst";
420 reset-names = "miphy-sw-rst";
434 reset-names = "miphy-sw-rst";
601 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
625 "sw-rst",
626 "pwr-rst";
H A Dsocfpga.dtsi8 #include <dt-bindings/reset/altr,rst-mgr.h>
479 resets = <&rst EMAC0_RESET>;
495 resets = <&rst EMAC1_RESET>;
739 rst: rstmgr@ffd05000 { label
741 compatible = "altr,rst-mgr";
H A Darmada-388-clearfog.dts271 /* int: mpp22 rst: mpp29 */
474 MPP29: gpio x mikro rst
501 MPP53: tdm:rst
/rk3399_rockchip-uboot/drivers/adc/
H A Drockchip-saradc-v2.c103 struct reset_ctl rst; member
145 reset_assert(&priv->rst); in rockchip_saradc_start_channel()
147 reset_deassert(&priv->rst); in rockchip_saradc_start_channel()
182 ret = reset_get_by_name(dev, "saradc-apb", &priv->rst); in rockchip_saradc_probe()
/rk3399_rockchip-uboot/drivers/misc/
H A Drockchip_decompress.c87 struct reset_ctl rst; member
107 reset_assert(&priv->rst); in rockchip_decom_start()
109 reset_deassert(&priv->rst); in rockchip_decom_start()
257 ret = reset_get_by_name(dev, "dresetn", &priv->rst); in rockchip_decom_probe()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c183 writel(0, &cpucfg->cpu[cpu].rst); in sunxi_cpu_power_off()
259 writel(0, &cpucfg->cpu[cpu].rst); in psci_cpu_on()
271 writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst); in psci_cpu_on()
/rk3399_rockchip-uboot/drivers/i2c/
H A Di2c-uniphier-f.c50 u32 rst; /* reset control */ member
79 writel(I2C_RST_RST, &regs->rst); in reset_bus()
80 ret = readl_poll_timeout(&regs->rst, val, !(val & I2C_RST_RST), 1); in reset_bus()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A Dcpucfg.h18 u32 rst; /* base + 0x0 */ member
/rk3399_rockchip-uboot/drivers/rkflash/
H A Dnandc.h98 unsigned rst : 1; member
147 unsigned rst : 1; member
H A Dnandc.c144 fl_reg.V6.rst = 1; in nandc_bch_sel()
175 tmp.V6.rst = 1; in nandc_bch_sel()
/rk3399_rockchip-uboot/board/ti/dra7xx/
H A DREADME26 U-Boot # mmc rst-function 1 1

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