1*0299c90fSStefan Roese/* 2*0299c90fSStefan Roese * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828) 3*0299c90fSStefan Roese * 4*0299c90fSStefan Roese * Copyright (C) 2015 Russell King 5*0299c90fSStefan Roese * 6*0299c90fSStefan Roese * This board is in development; the contents of this file work with 7*0299c90fSStefan Roese * the A1 rev 2.0 of the board, which does not represent final 8*0299c90fSStefan Roese * production board. Things will change, don't expect this file to 9*0299c90fSStefan Roese * remain compatible info the future. 10*0299c90fSStefan Roese * 11*0299c90fSStefan Roese * This file is dual-licensed: you can use it either under the terms 12*0299c90fSStefan Roese * of the GPL or the X11 license, at your option. Note that this dual 13*0299c90fSStefan Roese * licensing only applies to this file, and not this project as a 14*0299c90fSStefan Roese * whole. 15*0299c90fSStefan Roese * 16*0299c90fSStefan Roese * a) This file is free software; you can redistribute it and/or 17*0299c90fSStefan Roese * modify it under the terms of the GNU General Public License 18*0299c90fSStefan Roese * version 2 as published by the Free Software Foundation. 19*0299c90fSStefan Roese * 20*0299c90fSStefan Roese * This file is distributed in the hope that it will be useful 21*0299c90fSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 22*0299c90fSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23*0299c90fSStefan Roese * GNU General Public License for more details. 24*0299c90fSStefan Roese * 25*0299c90fSStefan Roese * Or, alternatively 26*0299c90fSStefan Roese * 27*0299c90fSStefan Roese * b) Permission is hereby granted, free of charge, to any person 28*0299c90fSStefan Roese * obtaining a copy of this software and associated documentation 29*0299c90fSStefan Roese * files (the "Software"), to deal in the Software without 30*0299c90fSStefan Roese * restriction, including without limitation the rights to use 31*0299c90fSStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 32*0299c90fSStefan Roese * sell copies of the Software, and to permit persons to whom the 33*0299c90fSStefan Roese * Software is furnished to do so, subject to the following 34*0299c90fSStefan Roese * conditions: 35*0299c90fSStefan Roese * 36*0299c90fSStefan Roese * The above copyright notice and this permission notice shall be 37*0299c90fSStefan Roese * included in all copies or substantial portions of the Software. 38*0299c90fSStefan Roese * 39*0299c90fSStefan Roese * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 40*0299c90fSStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41*0299c90fSStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42*0299c90fSStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43*0299c90fSStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 44*0299c90fSStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45*0299c90fSStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46*0299c90fSStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 47*0299c90fSStefan Roese */ 48*0299c90fSStefan Roese 49*0299c90fSStefan Roese/dts-v1/; 50*0299c90fSStefan Roese#include <dt-bindings/input/input.h> 51*0299c90fSStefan Roese#include <dt-bindings/gpio/gpio.h> 52*0299c90fSStefan Roese#include "armada-388.dtsi" 53*0299c90fSStefan Roese 54*0299c90fSStefan Roese/ { 55*0299c90fSStefan Roese model = "SolidRun Clearfog A1"; 56*0299c90fSStefan Roese compatible = "solidrun,clearfog-a1", "marvell,armada388", 57*0299c90fSStefan Roese "marvell,armada385", "marvell,armada380"; 58*0299c90fSStefan Roese 59*0299c90fSStefan Roese aliases { 60*0299c90fSStefan Roese /* So that mvebu u-boot can update the MAC addresses */ 61*0299c90fSStefan Roese ethernet1 = ð0; 62*0299c90fSStefan Roese ethernet2 = ð1; 63*0299c90fSStefan Roese ethernet3 = ð2; 64*0299c90fSStefan Roese }; 65*0299c90fSStefan Roese 66*0299c90fSStefan Roese chosen { 67*0299c90fSStefan Roese stdout-path = "serial0:115200n8"; 68*0299c90fSStefan Roese }; 69*0299c90fSStefan Roese 70*0299c90fSStefan Roese memory { 71*0299c90fSStefan Roese device_type = "memory"; 72*0299c90fSStefan Roese reg = <0x00000000 0x10000000>; /* 256 MB */ 73*0299c90fSStefan Roese }; 74*0299c90fSStefan Roese 75*0299c90fSStefan Roese reg_3p3v: regulator-3p3v { 76*0299c90fSStefan Roese compatible = "regulator-fixed"; 77*0299c90fSStefan Roese regulator-name = "3P3V"; 78*0299c90fSStefan Roese regulator-min-microvolt = <3300000>; 79*0299c90fSStefan Roese regulator-max-microvolt = <3300000>; 80*0299c90fSStefan Roese regulator-always-on; 81*0299c90fSStefan Roese }; 82*0299c90fSStefan Roese 83*0299c90fSStefan Roese soc { 84*0299c90fSStefan Roese ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 85*0299c90fSStefan Roese MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 86*0299c90fSStefan Roese MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 87*0299c90fSStefan Roese MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; 88*0299c90fSStefan Roese 89*0299c90fSStefan Roese internal-regs { 90*0299c90fSStefan Roese ethernet@30000 { 91*0299c90fSStefan Roese mac-address = [00 50 43 02 02 02]; 92*0299c90fSStefan Roese phy-mode = "sgmii"; 93*0299c90fSStefan Roese status = "okay"; 94*0299c90fSStefan Roese 95*0299c90fSStefan Roese fixed-link { 96*0299c90fSStefan Roese speed = <1000>; 97*0299c90fSStefan Roese full-duplex; 98*0299c90fSStefan Roese }; 99*0299c90fSStefan Roese }; 100*0299c90fSStefan Roese 101*0299c90fSStefan Roese ethernet@34000 { 102*0299c90fSStefan Roese mac-address = [00 50 43 02 02 03]; 103*0299c90fSStefan Roese managed = "in-band-status"; 104*0299c90fSStefan Roese phy-mode = "sgmii"; 105*0299c90fSStefan Roese status = "okay"; 106*0299c90fSStefan Roese }; 107*0299c90fSStefan Roese 108*0299c90fSStefan Roese ethernet@70000 { 109*0299c90fSStefan Roese mac-address = [00 50 43 02 02 01]; 110*0299c90fSStefan Roese pinctrl-0 = <&ge0_rgmii_pins>; 111*0299c90fSStefan Roese pinctrl-names = "default"; 112*0299c90fSStefan Roese phy = <&phy_dedicated>; 113*0299c90fSStefan Roese phy-mode = "rgmii-id"; 114*0299c90fSStefan Roese status = "okay"; 115*0299c90fSStefan Roese }; 116*0299c90fSStefan Roese 117*0299c90fSStefan Roese i2c@11000 { 118*0299c90fSStefan Roese /* Is there anything on this? */ 119*0299c90fSStefan Roese clock-frequency = <100000>; 120*0299c90fSStefan Roese pinctrl-0 = <&i2c0_pins>; 121*0299c90fSStefan Roese pinctrl-names = "default"; 122*0299c90fSStefan Roese status = "okay"; 123*0299c90fSStefan Roese 124*0299c90fSStefan Roese /* 125*0299c90fSStefan Roese * PCA9655 GPIO expander, up to 1MHz clock. 126*0299c90fSStefan Roese * 0-CON3 CLKREQ# 127*0299c90fSStefan Roese * 1-CON3 PERST# 128*0299c90fSStefan Roese * 2-CON2 PERST# 129*0299c90fSStefan Roese * 3-CON3 W_DISABLE 130*0299c90fSStefan Roese * 4-CON2 CLKREQ# 131*0299c90fSStefan Roese * 5-USB3 overcurrent 132*0299c90fSStefan Roese * 6-USB3 power 133*0299c90fSStefan Roese * 7-CON2 W_DISABLE 134*0299c90fSStefan Roese * 8-JP4 P1 135*0299c90fSStefan Roese * 9-JP4 P4 136*0299c90fSStefan Roese * 10-JP4 P5 137*0299c90fSStefan Roese * 11-m.2 DEVSLP 138*0299c90fSStefan Roese * 12-SFP_LOS 139*0299c90fSStefan Roese * 13-SFP_TX_FAULT 140*0299c90fSStefan Roese * 14-SFP_TX_DISABLE 141*0299c90fSStefan Roese * 15-SFP_MOD_DEF0 142*0299c90fSStefan Roese */ 143*0299c90fSStefan Roese expander0: gpio-expander@20 { 144*0299c90fSStefan Roese /* 145*0299c90fSStefan Roese * This is how it should be: 146*0299c90fSStefan Roese * compatible = "onnn,pca9655", 147*0299c90fSStefan Roese * "nxp,pca9555"; 148*0299c90fSStefan Roese * but you can't do this because of 149*0299c90fSStefan Roese * the way I2C works. 150*0299c90fSStefan Roese */ 151*0299c90fSStefan Roese compatible = "nxp,pca9555"; 152*0299c90fSStefan Roese gpio-controller; 153*0299c90fSStefan Roese #gpio-cells = <2>; 154*0299c90fSStefan Roese reg = <0x20>; 155*0299c90fSStefan Roese 156*0299c90fSStefan Roese pcie1_0_clkreq { 157*0299c90fSStefan Roese gpio-hog; 158*0299c90fSStefan Roese gpios = <0 GPIO_ACTIVE_LOW>; 159*0299c90fSStefan Roese input; 160*0299c90fSStefan Roese line-name = "pcie1.0-clkreq"; 161*0299c90fSStefan Roese }; 162*0299c90fSStefan Roese pcie1_0_w_disable { 163*0299c90fSStefan Roese gpio-hog; 164*0299c90fSStefan Roese gpios = <3 GPIO_ACTIVE_LOW>; 165*0299c90fSStefan Roese output-low; 166*0299c90fSStefan Roese line-name = "pcie1.0-w-disable"; 167*0299c90fSStefan Roese }; 168*0299c90fSStefan Roese pcie2_0_clkreq { 169*0299c90fSStefan Roese gpio-hog; 170*0299c90fSStefan Roese gpios = <4 GPIO_ACTIVE_LOW>; 171*0299c90fSStefan Roese input; 172*0299c90fSStefan Roese line-name = "pcie2.0-clkreq"; 173*0299c90fSStefan Roese }; 174*0299c90fSStefan Roese pcie2_0_w_disable { 175*0299c90fSStefan Roese gpio-hog; 176*0299c90fSStefan Roese gpios = <7 GPIO_ACTIVE_LOW>; 177*0299c90fSStefan Roese output-low; 178*0299c90fSStefan Roese line-name = "pcie2.0-w-disable"; 179*0299c90fSStefan Roese }; 180*0299c90fSStefan Roese usb3_ilimit { 181*0299c90fSStefan Roese gpio-hog; 182*0299c90fSStefan Roese gpios = <5 GPIO_ACTIVE_LOW>; 183*0299c90fSStefan Roese input; 184*0299c90fSStefan Roese line-name = "usb3-current-limit"; 185*0299c90fSStefan Roese }; 186*0299c90fSStefan Roese usb3_power { 187*0299c90fSStefan Roese gpio-hog; 188*0299c90fSStefan Roese gpios = <6 GPIO_ACTIVE_HIGH>; 189*0299c90fSStefan Roese output-high; 190*0299c90fSStefan Roese line-name = "usb3-power"; 191*0299c90fSStefan Roese }; 192*0299c90fSStefan Roese m2_devslp { 193*0299c90fSStefan Roese gpio-hog; 194*0299c90fSStefan Roese gpios = <11 GPIO_ACTIVE_HIGH>; 195*0299c90fSStefan Roese output-low; 196*0299c90fSStefan Roese line-name = "m.2 devslp"; 197*0299c90fSStefan Roese }; 198*0299c90fSStefan Roese }; 199*0299c90fSStefan Roese 200*0299c90fSStefan Roese /* The MCP3021 is 100kHz clock only */ 201*0299c90fSStefan Roese mikrobus_adc: mcp3021@4c { 202*0299c90fSStefan Roese compatible = "microchip,mcp3021"; 203*0299c90fSStefan Roese reg = <0x4c>; 204*0299c90fSStefan Roese }; 205*0299c90fSStefan Roese 206*0299c90fSStefan Roese /* Also something at 0x64 */ 207*0299c90fSStefan Roese }; 208*0299c90fSStefan Roese 209*0299c90fSStefan Roese i2c@11100 { 210*0299c90fSStefan Roese /* 211*0299c90fSStefan Roese * Routed to SFP, mikrobus, and PCIe. 212*0299c90fSStefan Roese * SFP limits this to 100kHz, and requires 213*0299c90fSStefan Roese * an AT24C01A/02/04 with address pins tied 214*0299c90fSStefan Roese * low, which takes addresses 0x50 and 0x51. 215*0299c90fSStefan Roese * Mikrobus doesn't specify beyond an I2C 216*0299c90fSStefan Roese * bus being present. 217*0299c90fSStefan Roese * PCIe uses ARP to assign addresses, or 218*0299c90fSStefan Roese * 0x63-0x64. 219*0299c90fSStefan Roese */ 220*0299c90fSStefan Roese clock-frequency = <100000>; 221*0299c90fSStefan Roese pinctrl-0 = <&clearfog_i2c1_pins>; 222*0299c90fSStefan Roese pinctrl-names = "default"; 223*0299c90fSStefan Roese status = "okay"; 224*0299c90fSStefan Roese }; 225*0299c90fSStefan Roese 226*0299c90fSStefan Roese mdio@72004 { 227*0299c90fSStefan Roese pinctrl-0 = <&mdio_pins>; 228*0299c90fSStefan Roese pinctrl-names = "default"; 229*0299c90fSStefan Roese 230*0299c90fSStefan Roese phy_dedicated: ethernet-phy@0 { 231*0299c90fSStefan Roese /* 232*0299c90fSStefan Roese * Annoyingly, the marvell phy driver 233*0299c90fSStefan Roese * configures the LED register, rather 234*0299c90fSStefan Roese * than preserving reset-loaded setting. 235*0299c90fSStefan Roese * We undo that rubbish here. 236*0299c90fSStefan Roese */ 237*0299c90fSStefan Roese marvell,reg-init = <3 16 0 0x101e>; 238*0299c90fSStefan Roese reg = <0>; 239*0299c90fSStefan Roese }; 240*0299c90fSStefan Roese }; 241*0299c90fSStefan Roese 242*0299c90fSStefan Roese pinctrl@18000 { 243*0299c90fSStefan Roese clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { 244*0299c90fSStefan Roese marvell,pins = "mpp46"; 245*0299c90fSStefan Roese marvell,function = "ref"; 246*0299c90fSStefan Roese }; 247*0299c90fSStefan Roese clearfog_dsa0_pins: clearfog-dsa0-pins { 248*0299c90fSStefan Roese marvell,pins = "mpp23", "mpp41"; 249*0299c90fSStefan Roese marvell,function = "gpio"; 250*0299c90fSStefan Roese }; 251*0299c90fSStefan Roese clearfog_i2c1_pins: i2c1-pins { 252*0299c90fSStefan Roese /* SFP, PCIe, mSATA, mikrobus */ 253*0299c90fSStefan Roese marvell,pins = "mpp26", "mpp27"; 254*0299c90fSStefan Roese marvell,function = "i2c1"; 255*0299c90fSStefan Roese }; 256*0299c90fSStefan Roese clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { 257*0299c90fSStefan Roese marvell,pins = "mpp20"; 258*0299c90fSStefan Roese marvell,function = "gpio"; 259*0299c90fSStefan Roese }; 260*0299c90fSStefan Roese clearfog_sdhci_pins: clearfog-sdhci-pins { 261*0299c90fSStefan Roese marvell,pins = "mpp21", "mpp28", 262*0299c90fSStefan Roese "mpp37", "mpp38", 263*0299c90fSStefan Roese "mpp39", "mpp40"; 264*0299c90fSStefan Roese marvell,function = "sd0"; 265*0299c90fSStefan Roese }; 266*0299c90fSStefan Roese clearfog_spi1_cs_pins: spi1-cs-pins { 267*0299c90fSStefan Roese marvell,pins = "mpp55"; 268*0299c90fSStefan Roese marvell,function = "spi1"; 269*0299c90fSStefan Roese }; 270*0299c90fSStefan Roese mikro_pins: mikro-pins { 271*0299c90fSStefan Roese /* int: mpp22 rst: mpp29 */ 272*0299c90fSStefan Roese marvell,pins = "mpp22", "mpp29"; 273*0299c90fSStefan Roese marvell,function = "gpio"; 274*0299c90fSStefan Roese }; 275*0299c90fSStefan Roese mikro_spi_pins: mikro-spi-pins { 276*0299c90fSStefan Roese marvell,pins = "mpp43"; 277*0299c90fSStefan Roese marvell,function = "spi1"; 278*0299c90fSStefan Roese }; 279*0299c90fSStefan Roese mikro_uart_pins: mikro-uart-pins { 280*0299c90fSStefan Roese marvell,pins = "mpp24", "mpp25"; 281*0299c90fSStefan Roese marvell,function = "ua1"; 282*0299c90fSStefan Roese }; 283*0299c90fSStefan Roese rear_button_pins: rear-button-pins { 284*0299c90fSStefan Roese marvell,pins = "mpp34"; 285*0299c90fSStefan Roese marvell,function = "gpio"; 286*0299c90fSStefan Roese }; 287*0299c90fSStefan Roese }; 288*0299c90fSStefan Roese 289*0299c90fSStefan Roese rtc@a3800 { 290*0299c90fSStefan Roese /* 291*0299c90fSStefan Roese * If the rtc doesn't work, run "date reset" 292*0299c90fSStefan Roese * twice in u-boot. 293*0299c90fSStefan Roese */ 294*0299c90fSStefan Roese status = "okay"; 295*0299c90fSStefan Roese }; 296*0299c90fSStefan Roese 297*0299c90fSStefan Roese sata@a8000 { 298*0299c90fSStefan Roese /* pinctrl? */ 299*0299c90fSStefan Roese status = "okay"; 300*0299c90fSStefan Roese }; 301*0299c90fSStefan Roese 302*0299c90fSStefan Roese sata@e0000 { 303*0299c90fSStefan Roese /* pinctrl? */ 304*0299c90fSStefan Roese status = "okay"; 305*0299c90fSStefan Roese }; 306*0299c90fSStefan Roese 307*0299c90fSStefan Roese sdhci@d8000 { 308*0299c90fSStefan Roese bus-width = <4>; 309*0299c90fSStefan Roese cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; 310*0299c90fSStefan Roese no-1-8-v; 311*0299c90fSStefan Roese pinctrl-0 = <&clearfog_sdhci_pins 312*0299c90fSStefan Roese &clearfog_sdhci_cd_pins>; 313*0299c90fSStefan Roese pinctrl-names = "default"; 314*0299c90fSStefan Roese status = "okay"; 315*0299c90fSStefan Roese vmmc = <®_3p3v>; 316*0299c90fSStefan Roese wp-inverted; 317*0299c90fSStefan Roese }; 318*0299c90fSStefan Roese 319*0299c90fSStefan Roese serial@12000 { 320*0299c90fSStefan Roese pinctrl-0 = <&uart0_pins>; 321*0299c90fSStefan Roese pinctrl-names = "default"; 322*0299c90fSStefan Roese status = "okay"; 323*0299c90fSStefan Roese u-boot,dm-pre-reloc; 324*0299c90fSStefan Roese }; 325*0299c90fSStefan Roese 326*0299c90fSStefan Roese serial@12100 { 327*0299c90fSStefan Roese /* mikrobus uart */ 328*0299c90fSStefan Roese pinctrl-0 = <&mikro_uart_pins>; 329*0299c90fSStefan Roese pinctrl-names = "default"; 330*0299c90fSStefan Roese status = "okay"; 331*0299c90fSStefan Roese }; 332*0299c90fSStefan Roese 333*0299c90fSStefan Roese spi@10680 { 334*0299c90fSStefan Roese /* 335*0299c90fSStefan Roese * We don't seem to have the W25Q32 on the 336*0299c90fSStefan Roese * A1 Rev 2.0 boards, so disable SPI. 337*0299c90fSStefan Roese * CS0: W25Q32 (doesn't appear to be present) 338*0299c90fSStefan Roese * CS1: 339*0299c90fSStefan Roese * CS2: mikrobus 340*0299c90fSStefan Roese */ 341*0299c90fSStefan Roese pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; 342*0299c90fSStefan Roese pinctrl-names = "default"; 343*0299c90fSStefan Roese status = "okay"; 344*0299c90fSStefan Roese 345*0299c90fSStefan Roese spi-flash@0 { 346*0299c90fSStefan Roese #address-cells = <1>; 347*0299c90fSStefan Roese #size-cells = <0>; 348*0299c90fSStefan Roese compatible = "w25q32", "jedec,spi-nor"; 349*0299c90fSStefan Roese reg = <0>; /* Chip select 0 */ 350*0299c90fSStefan Roese spi-max-frequency = <3000000>; 351*0299c90fSStefan Roese status = "disabled"; 352*0299c90fSStefan Roese }; 353*0299c90fSStefan Roese }; 354*0299c90fSStefan Roese 355*0299c90fSStefan Roese usb3@f8000 { 356*0299c90fSStefan Roese status = "okay"; 357*0299c90fSStefan Roese }; 358*0299c90fSStefan Roese }; 359*0299c90fSStefan Roese 360*0299c90fSStefan Roese pcie-controller { 361*0299c90fSStefan Roese status = "okay"; 362*0299c90fSStefan Roese /* 363*0299c90fSStefan Roese * The two PCIe units are accessible through 364*0299c90fSStefan Roese * the mini-PCIe connectors on the board. 365*0299c90fSStefan Roese */ 366*0299c90fSStefan Roese pcie@2,0 { 367*0299c90fSStefan Roese /* Port 1, Lane 0. CONN3, nearest power. */ 368*0299c90fSStefan Roese reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; 369*0299c90fSStefan Roese status = "okay"; 370*0299c90fSStefan Roese }; 371*0299c90fSStefan Roese pcie@3,0 { 372*0299c90fSStefan Roese /* Port 2, Lane 0. CONN2, nearest CPU. */ 373*0299c90fSStefan Roese reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; 374*0299c90fSStefan Roese status = "okay"; 375*0299c90fSStefan Roese }; 376*0299c90fSStefan Roese }; 377*0299c90fSStefan Roese }; 378*0299c90fSStefan Roese 379*0299c90fSStefan Roese sfp: sfp { 380*0299c90fSStefan Roese compatible = "sff,sfp"; 381*0299c90fSStefan Roese i2c-bus = <&i2c1>; 382*0299c90fSStefan Roese los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; 383*0299c90fSStefan Roese moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; 384*0299c90fSStefan Roese sfp,ethernet = <ð2>; 385*0299c90fSStefan Roese tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; 386*0299c90fSStefan Roese tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; 387*0299c90fSStefan Roese }; 388*0299c90fSStefan Roese 389*0299c90fSStefan Roese dsa@0 { 390*0299c90fSStefan Roese compatible = "marvell,dsa"; 391*0299c90fSStefan Roese dsa,ethernet = <ð1>; 392*0299c90fSStefan Roese dsa,mii-bus = <&mdio>; 393*0299c90fSStefan Roese pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; 394*0299c90fSStefan Roese pinctrl-names = "default"; 395*0299c90fSStefan Roese #address-cells = <2>; 396*0299c90fSStefan Roese #size-cells = <0>; 397*0299c90fSStefan Roese 398*0299c90fSStefan Roese switch@0 { 399*0299c90fSStefan Roese #address-cells = <1>; 400*0299c90fSStefan Roese #size-cells = <0>; 401*0299c90fSStefan Roese reg = <4 0>; 402*0299c90fSStefan Roese 403*0299c90fSStefan Roese port@0 { 404*0299c90fSStefan Roese reg = <0>; 405*0299c90fSStefan Roese label = "lan1"; 406*0299c90fSStefan Roese }; 407*0299c90fSStefan Roese 408*0299c90fSStefan Roese port@1 { 409*0299c90fSStefan Roese reg = <1>; 410*0299c90fSStefan Roese label = "lan2"; 411*0299c90fSStefan Roese }; 412*0299c90fSStefan Roese 413*0299c90fSStefan Roese port@2 { 414*0299c90fSStefan Roese reg = <2>; 415*0299c90fSStefan Roese label = "lan3"; 416*0299c90fSStefan Roese }; 417*0299c90fSStefan Roese 418*0299c90fSStefan Roese port@3 { 419*0299c90fSStefan Roese reg = <3>; 420*0299c90fSStefan Roese label = "lan4"; 421*0299c90fSStefan Roese }; 422*0299c90fSStefan Roese 423*0299c90fSStefan Roese port@4 { 424*0299c90fSStefan Roese reg = <4>; 425*0299c90fSStefan Roese label = "lan5"; 426*0299c90fSStefan Roese }; 427*0299c90fSStefan Roese 428*0299c90fSStefan Roese port@5 { 429*0299c90fSStefan Roese reg = <5>; 430*0299c90fSStefan Roese label = "cpu"; 431*0299c90fSStefan Roese }; 432*0299c90fSStefan Roese 433*0299c90fSStefan Roese port@6 { 434*0299c90fSStefan Roese /* 88E1512 external phy */ 435*0299c90fSStefan Roese reg = <6>; 436*0299c90fSStefan Roese label = "lan6"; 437*0299c90fSStefan Roese fixed-link { 438*0299c90fSStefan Roese speed = <1000>; 439*0299c90fSStefan Roese full-duplex; 440*0299c90fSStefan Roese }; 441*0299c90fSStefan Roese }; 442*0299c90fSStefan Roese }; 443*0299c90fSStefan Roese }; 444*0299c90fSStefan Roese 445*0299c90fSStefan Roese gpio-keys { 446*0299c90fSStefan Roese compatible = "gpio-keys"; 447*0299c90fSStefan Roese pinctrl-0 = <&rear_button_pins>; 448*0299c90fSStefan Roese pinctrl-names = "default"; 449*0299c90fSStefan Roese 450*0299c90fSStefan Roese button_0 { 451*0299c90fSStefan Roese /* The rear SW3 button */ 452*0299c90fSStefan Roese label = "Rear Button"; 453*0299c90fSStefan Roese gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; 454*0299c90fSStefan Roese linux,can-disable; 455*0299c90fSStefan Roese linux,code = <BTN_0>; 456*0299c90fSStefan Roese }; 457*0299c90fSStefan Roese }; 458*0299c90fSStefan Roese}; 459*0299c90fSStefan Roese 460*0299c90fSStefan Roese/* 461*0299c90fSStefan Roese+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011 462*0299c90fSStefan RoeseMPP18: gpio ? (pca9655 int?) 463*0299c90fSStefan RoeseMPP19: gpio ? (clkreq?) 464*0299c90fSStefan RoeseMPP20: gpio ? (sd0 detect) 465*0299c90fSStefan RoeseMPP21: sd0:cmd x sd0 466*0299c90fSStefan RoeseMPP22: gpio x mikro int 467*0299c90fSStefan RoeseMPP23: gpio x switch irq 468*0299c90fSStefan Roese+#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333 469*0299c90fSStefan RoeseMPP24: ua1:rxd x mikro rx 470*0299c90fSStefan RoeseMPP25: ua1:txd x mikro tx 471*0299c90fSStefan RoeseMPP26: i2c1:sck x mikro sck 472*0299c90fSStefan RoeseMPP27: i2c1:sda x mikro sda 473*0299c90fSStefan RoeseMPP28: sd0:clk x sd0 474*0299c90fSStefan RoeseMPP29: gpio x mikro rst 475*0299c90fSStefan RoeseMPP30: ge1:txd2 ? (config) 476*0299c90fSStefan RoeseMPP31: ge1:txd3 ? (config) 477*0299c90fSStefan Roese+#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002 478*0299c90fSStefan RoeseMPP32: ge1:txctl ? (unused) 479*0299c90fSStefan RoeseMPP33: gpio ? (pic_com0) 480*0299c90fSStefan RoeseMPP34: gpio x rear button (pic_com1) 481*0299c90fSStefan RoeseMPP35: gpio ? (pic_com2) 482*0299c90fSStefan RoeseMPP36: gpio ? (unused) 483*0299c90fSStefan RoeseMPP37: sd0:d3 x sd0 484*0299c90fSStefan RoeseMPP38: sd0:d0 x sd0 485*0299c90fSStefan RoeseMPP39: sd0:d1 x sd0 486*0299c90fSStefan Roese+#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004 487*0299c90fSStefan RoeseMPP40: sd0:d2 x sd0 488*0299c90fSStefan RoeseMPP41: gpio x switch reset 489*0299c90fSStefan RoeseMPP42: gpio ? sw1-1 490*0299c90fSStefan RoeseMPP43: spi1:cs2 x mikro cs 491*0299c90fSStefan RoeseMPP44: sata3:prsnt ? (unused) 492*0299c90fSStefan RoeseMPP45: ref:clk_out0 ? 493*0299c90fSStefan RoeseMPP46: ref:clk_out1 x switch clk 494*0299c90fSStefan RoeseMPP47: 4 ? (unused) 495*0299c90fSStefan Roese+#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333 496*0299c90fSStefan RoeseMPP48: tdm:pclk 497*0299c90fSStefan RoeseMPP49: tdm:fsync 498*0299c90fSStefan RoeseMPP50: tdm:drx 499*0299c90fSStefan RoeseMPP51: tdm:dtx 500*0299c90fSStefan RoeseMPP52: tdm:int 501*0299c90fSStefan RoeseMPP53: tdm:rst 502*0299c90fSStefan RoeseMPP54: gpio ? (pwm) 503*0299c90fSStefan RoeseMPP55: spi1:cs1 x slic 504*0299c90fSStefan Roese+#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444 505*0299c90fSStefan RoeseMPP56: spi1:mosi x mikro mosi 506*0299c90fSStefan RoeseMPP57: spi1:sck x mikro sck 507*0299c90fSStefan RoeseMPP58: spi1:miso x mikro miso 508*0299c90fSStefan RoeseMPP59: spi1:cs0 x w25q32 509*0299c90fSStefan Roese*/ 510