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Searched refs:reg_data (Results 1 – 25 of 32) sorted by relevance

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/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_a38x_mc_static.h15 static struct reg_data ddr3_customer_800[] = {
52 struct reg_data ddr3_a38x_933[MV_MAX_DDR3_STATIC_SIZE] = {
87 static struct reg_data ddr3_a38x_800[] = {
122 static struct reg_data ddr3_a38x_667[] = {
172 static struct reg_data ddr3_a38x_533[] = {
H A Dddr3_training_ip_engine.c187 reg_data, pup_id; in ddr3_tip_ip_training() local
248 reg_data = (direction == OPER_READ) ? 0 : (0x3 << 30); in ddr3_tip_ip_training()
249 reg_data |= (direction == OPER_READ) ? 0x60 : 0xfa; in ddr3_tip_ip_training()
252 ODPG_WRITE_READ_MODE_ENABLE_REG, reg_data, in ddr3_tip_ip_training()
254 reg_data = (edge_comp == EDGE_PF || edge_comp == EDGE_FP) ? 0 : 1 << 6; in ddr3_tip_ip_training()
255 reg_data |= (edge_comp == EDGE_PF || edge_comp == EDGE_PFP) ? in ddr3_tip_ip_training()
260 reg_data |= 0xe << 14; in ddr3_tip_ip_training()
262 reg_data |= pup_num << 14; in ddr3_tip_ip_training()
266 reg_data |= (0 << 20); in ddr3_tip_ip_training()
268 reg_data |= (0 << 20); in ddr3_tip_ip_training()
[all …]
H A Dddr3_debug.c489 u32 reg_data; in ddr3_tip_print_stability_log() local
547 csindex, &reg_data); in ddr3_tip_print_stability_log()
548 printf("%d,%d,", (reg_data & 0x1f), in ddr3_tip_print_stability_log()
549 ((reg_data & 0x3e0) >> 5)); in ddr3_tip_print_stability_log()
555 csindex * 4, &reg_data); in ddr3_tip_print_stability_log()
557 (reg_data & 0x1f) + in ddr3_tip_print_stability_log()
558 ((reg_data & 0x1c0) >> 6) * 32, in ddr3_tip_print_stability_log()
559 (reg_data & 0x1f), in ddr3_tip_print_stability_log()
560 (reg_data & 0x1c0) >> 6); in ddr3_tip_print_stability_log()
575 &reg_data); in ddr3_tip_print_stability_log()
[all …]
H A Dddr3_training_leveling.c959 u32 reg_data = 0, iter, if_id, bus_cnt; in ddr3_tip_dynamic_write_leveling() local
1067 reg_data)); in ddr3_tip_dynamic_write_leveling()
1075 &reg_data, (1 << 2))); in ddr3_tip_dynamic_write_leveling()
1076 if (reg_data != 0) { in ddr3_tip_dynamic_write_leveling()
1080 if_id, reg_data)); in ddr3_tip_dynamic_write_leveling()
1096 reg_data)); in ddr3_tip_dynamic_write_leveling()
1104 reg_data = data_read[if_id]; in ddr3_tip_dynamic_write_leveling()
1105 if (reg_data != 0) { in ddr3_tip_dynamic_write_leveling()
1109 if_id, reg_data)); in ddr3_tip_dynamic_write_leveling()
1127 reg_data = data_read[if_id]; in ddr3_tip_dynamic_write_leveling()
[all …]
H A Dddr3_training_ip_def.h167 struct reg_data { struct
169 u32 reg_data; argument
H A Dddr3_hws_hw_training.h13 u32 reg_data; member
H A Dddr3_training_ip_static.h28 struct reg_data *reg_config_arr);
H A Dddr3_training_static.c35 static reg_data *static_init_controller_config[HWS_MAX_DEVICE_NUM];
68 int ddr3_tip_init_specific_reg_config(u32 dev_num, reg_data *reg_config_arr) in ddr3_tip_init_specific_reg_config()
413 reg_data, in ddr3_tip_static_init_controller()
H A Dddr3_training_hw_algo.c122 u32 reg_data; in get_valid_win_rx() local
135 &reg_data)); in get_valid_win_rx()
136 res[i] = (reg_data >> RESULT_DB_PHY_REG_RX_OFFSET) & 0x1f; in get_valid_win_rx()
H A Dddr3_init.c59 struct reg_data *regs;
568 config_table_ptr[i].reg_data); in ddr3_new_tip_dlb_config()
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/serdes/a38x/
H A Dseq_exec.c33 u32 unit_base_reg, unit_offset, data, mask, reg_data, reg_addr; in write_op_execute() local
55 reg_data = reg_read(reg_addr); in write_op_execute()
56 reg_data &= (~mask); in write_op_execute()
60 reg_data |= data; in write_op_execute()
61 reg_write(reg_addr, reg_data); in write_op_execute()
64 printf(" - 0x%x\n", reg_data); in write_op_execute()
88 u32 reg_addr, reg_data; in poll_op_execute() local
114 reg_data = reg_read(reg_addr) & mask; in poll_op_execute()
117 } while ((reg_data != data) && (poll_counter < num_of_loops)); in poll_op_execute()
119 if ((poll_counter >= num_of_loops) && (reg_data != data)) { in poll_op_execute()
H A Dhigh_speed_env_spec.c1563 u32 reg_data; in serdes_pex_usb3_pipe_delay_w_a() local
1567 reg_data = reg_read(GENERAL_PURPOSE_RESERVED0_REG); in serdes_pex_usb3_pipe_delay_w_a()
1577 reg_data |= 1 << (7 + (serdes_num - 3)); in serdes_pex_usb3_pipe_delay_w_a()
1580 reg_data &= ~(1 << (7 + (serdes_num - 3))); in serdes_pex_usb3_pipe_delay_w_a()
1582 reg_write(GENERAL_PURPOSE_RESERVED0_REG, reg_data); in serdes_pex_usb3_pipe_delay_w_a()
1681 u32 reg_data; in serdes_power_up_ctrl() local
1723 reg_data = reg_read(SOC_CONTROL_REG1); in serdes_power_up_ctrl()
1725 reg_data |= 0x4000; in serdes_power_up_ctrl()
1727 reg_data &= ~0x4000; in serdes_power_up_ctrl()
1728 reg_write(SOC_CONTROL_REG1, reg_data); in serdes_power_up_ctrl()
[all …]
/rk3399_rockchip-uboot/drivers/phy/marvell/
H A Dcomphy_core.c59 u32 reg_data; in reg_set_silent() local
61 reg_data = readl(addr); in reg_set_silent()
62 reg_data &= ~mask; in reg_set_silent()
63 reg_data |= data; in reg_set_silent()
64 writel(reg_data, addr); in reg_set_silent()
78 u16 reg_data; in reg_set_silent16() local
80 reg_data = readw(addr); in reg_set_silent16()
81 reg_data &= ~mask; in reg_set_silent16()
82 reg_data |= data; in reg_set_silent16()
83 writew(reg_data, addr); in reg_set_silent16()
/rk3399_rockchip-uboot/drivers/gpio/
H A Dbcm6345_gpio.c21 void __iomem *reg_data; member
28 return !!(readl_be(priv->reg_data) & BIT(offset)); in bcm6345_gpio_get_value()
37 setbits_be32(priv->reg_data, BIT(offset)); in bcm6345_gpio_set_value()
39 clrbits_be32(priv->reg_data, BIT(offset)); in bcm6345_gpio_set_value()
105 priv->reg_data = ioremap(data_addr, data_size); in bcm6345_gpio_probe()
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Dvc.c94 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) in omap_vc_bypass_send_value() argument
105 reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK; in omap_vc_bypass_send_value()
110 reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT; in omap_vc_bypass_send_value()
/rk3399_rockchip-uboot/drivers/net/phy/
H A Dcortina.c128 char reg_data[0x50] = {0}; in cs4340_upload_firmware() local
209 memcpy(reg_data, &line_temp[i], column_cnt - i); in cs4340_upload_firmware()
211 strim(reg_data); in cs4340_upload_firmware()
213 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & in cs4340_upload_firmware()
/rk3399_rockchip-uboot/drivers/sound/
H A Dwm8994.c297 unsigned short reg_data; in wm8994_hw_params() local
390 if (wm8994_i2c_read(aif1_reg, &reg_data) != 0) { in wm8994_hw_params()
395 if ((channels == 1) && ((reg_data & 0x18) == 0x18)) in wm8994_hw_params()
658 unsigned short reg_data; in wm8994_device_init() local
663 ret = wm8994_i2c_read(WM8994_SOFTWARE_RESET, &reg_data); in wm8994_device_init()
669 if (reg_data == WM8994_ID) { in wm8994_device_init()
679 ret = wm8994_i2c_read(WM8994_CHIP_REVISION, &reg_data); in wm8994_device_init()
684 wm8994->revision = reg_data; in wm8994_device_init()
/rk3399_rockchip-uboot/drivers/net/
H A De1000.c1157 uint32_t reg_data = 0; in e1000_read_mac_addr() local
1167 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); in e1000_read_mac_addr()
1169 reg_data >>= 16; in e1000_read_mac_addr()
1171 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); in e1000_read_mac_addr()
1172 eeprom_data = reg_data & 0xffff; in e1000_read_mac_addr()
1638 uint32_t reg_data; in e1000_init_hw() local
1646 reg_data = E1000_READ_REG(hw, STATUS); in e1000_init_hw()
1647 reg_data &= ~0x80000000; in e1000_init_hw()
1648 E1000_WRITE_REG(hw, STATUS, reg_data); in e1000_init_hw()
1788 reg_data = E1000_READ_REG(hw, TCTL); in e1000_init_hw()
[all …]
H A Dxilinx_ll_temac.c84 int ll_temac_indirect_set(struct temac_reg *regs, u16 regn, u32 reg_data) in ll_temac_indirect_set() argument
86 out_be32(&regs->lsw, (reg_data & MLSW_MASK)); in ll_temac_indirect_set()
101 int ll_temac_indirect_get(struct temac_reg *regs, u16 regn, u32* reg_data) in ll_temac_indirect_get() argument
108 *reg_data = in_be32(&regs->lsw) & MLSW_MASK; in ll_temac_indirect_get()
H A Dks8851_mll.c190 u16 reg_data = 0; in ks_read_config() local
193 reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF; in ks_read_config()
194 reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8; in ks_read_config()
197 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED; in ks_read_config()
203 if (reg_data & CCR_8BIT) { in ks_read_config()
206 } else if (reg_data & CCR_16BIT) { in ks_read_config()
H A Dmvgbe.c183 u32 reg_data; in stop_queue() local
185 reg_data = readl(qreg); in stop_queue()
187 if (reg_data & 0xFF) { in stop_queue()
189 writel((reg_data << 8), qreg); in stop_queue()
197 reg_data = readl(qreg); in stop_queue()
199 while (reg_data & 0xFF); in stop_queue()
H A Dxilinx_ll_temac.h285 int ll_temac_indirect_set(struct temac_reg *regs, u16 regn, u32 reg_data);
288 int ll_temac_indirect_get(struct temac_reg *regs, u16 regn, u32* reg_data);
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap4/
H A Dsys_proto.h67 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap5/
H A Dsys_proto.h67 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
/rk3399_rockchip-uboot/include/power/
H A Drk801_pmic.h134 struct reg_data { struct

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