1*f1df9364SStefan Roese /* 2*f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 3*f1df9364SStefan Roese * 4*f1df9364SStefan Roese * SPDX-License-Identifier: GPL-2.0 5*f1df9364SStefan Roese */ 6*f1df9364SStefan Roese 7*f1df9364SStefan Roese #ifndef _DDR3_TRAINING_IP_STATIC_H_ 8*f1df9364SStefan Roese #define _DDR3_TRAINING_IP_STATIC_H_ 9*f1df9364SStefan Roese 10*f1df9364SStefan Roese #include "ddr3_training_ip_def.h" 11*f1df9364SStefan Roese #include "ddr3_training_ip.h" 12*f1df9364SStefan Roese 13*f1df9364SStefan Roese struct trip_delay_element { 14*f1df9364SStefan Roese u32 dqs_delay; /* DQS delay (m_sec) */ 15*f1df9364SStefan Roese u32 ck_delay; /* CK Delay (m_sec) */ 16*f1df9364SStefan Roese }; 17*f1df9364SStefan Roese 18*f1df9364SStefan Roese struct hws_tip_static_config_info { 19*f1df9364SStefan Roese u32 silicon_delay; 20*f1df9364SStefan Roese struct trip_delay_element *package_trace_arr; 21*f1df9364SStefan Roese struct trip_delay_element *board_trace_arr; 22*f1df9364SStefan Roese }; 23*f1df9364SStefan Roese 24*f1df9364SStefan Roese int ddr3_tip_run_static_alg(u32 dev_num, enum hws_ddr_freq freq); 25*f1df9364SStefan Roese int ddr3_tip_init_static_config_db( 26*f1df9364SStefan Roese u32 dev_num, struct hws_tip_static_config_info *static_config_info); 27*f1df9364SStefan Roese int ddr3_tip_init_specific_reg_config(u32 dev_num, 28*f1df9364SStefan Roese struct reg_data *reg_config_arr); 29*f1df9364SStefan Roese int ddr3_tip_static_phy_init_controller(u32 dev_num); 30*f1df9364SStefan Roese 31*f1df9364SStefan Roese #endif /* _DDR3_TRAINING_IP_STATIC_H_ */ 32