1*f1df9364SStefan Roese /* 2*f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 3*f1df9364SStefan Roese * 4*f1df9364SStefan Roese * SPDX-License-Identifier: GPL-2.0 5*f1df9364SStefan Roese */ 6*f1df9364SStefan Roese 7*f1df9364SStefan Roese #ifndef _DDR3_A38X_MC_STATIC_H 8*f1df9364SStefan Roese #define _DDR3_A38X_MC_STATIC_H 9*f1df9364SStefan Roese 10*f1df9364SStefan Roese #include "ddr3_a38x.h" 11*f1df9364SStefan Roese 12*f1df9364SStefan Roese #ifdef SUPPORT_STATIC_DUNIT_CONFIG 13*f1df9364SStefan Roese 14*f1df9364SStefan Roese #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT 15*f1df9364SStefan Roese static struct reg_data ddr3_customer_800[] = { 16*f1df9364SStefan Roese /* parameters for customer board (based on 800MHZ) */ 17*f1df9364SStefan Roese {0x1400, 0x7b00cc30, 0xffffffff}, 18*f1df9364SStefan Roese {0x1404, 0x36301820, 0xffffffff}, 19*f1df9364SStefan Roese {0x1408, 0x5415baab, 0xffffffff}, 20*f1df9364SStefan Roese {0x140c, 0x38411def, 0xffffffff}, 21*f1df9364SStefan Roese {0x1410, 0x18300000, 0xffffffff}, 22*f1df9364SStefan Roese {0x1414, 0x00000700, 0xffffffff}, 23*f1df9364SStefan Roese {0x1424, 0x0060f3ff, 0xffffffff}, 24*f1df9364SStefan Roese {0x1428, 0x0011a940, 0xffffffff}, 25*f1df9364SStefan Roese {0x142c, 0x28c5134, 0xffffffff}, 26*f1df9364SStefan Roese {0x1474, 0x00000000, 0xffffffff}, 27*f1df9364SStefan Roese {0x147c, 0x0000d771, 0xffffffff}, 28*f1df9364SStefan Roese {0x1494, 0x00030000, 0xffffffff}, 29*f1df9364SStefan Roese {0x149c, 0x00000300, 0xffffffff}, 30*f1df9364SStefan Roese {0x14a8, 0x00000000, 0xffffffff}, 31*f1df9364SStefan Roese {0x14cc, 0xbd09000d, 0xffffffff}, 32*f1df9364SStefan Roese {0x1504, 0xfffffff1, 0xffffffff}, 33*f1df9364SStefan Roese {0x150c, 0xffffffe5, 0xffffffff}, 34*f1df9364SStefan Roese {0x1514, 0x00000000, 0xffffffff}, 35*f1df9364SStefan Roese {0x151c, 0x00000000, 0xffffffff}, 36*f1df9364SStefan Roese {0x1538, 0x00000b0b, 0xffffffff}, 37*f1df9364SStefan Roese {0x153c, 0x00000c0c, 0xffffffff}, 38*f1df9364SStefan Roese {0x15d0, 0x00000670, 0xffffffff}, 39*f1df9364SStefan Roese {0x15d4, 0x00000046, 0xffffffff}, 40*f1df9364SStefan Roese {0x15d8, 0x00000010, 0xffffffff}, 41*f1df9364SStefan Roese {0x15dc, 0x00000000, 0xffffffff}, 42*f1df9364SStefan Roese {0x15e0, 0x00000023, 0xffffffff}, 43*f1df9364SStefan Roese {0x15e4, 0x00203c18, 0xffffffff}, 44*f1df9364SStefan Roese {0x15ec, 0xf8000019, 0xffffffff}, 45*f1df9364SStefan Roese {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */ 46*f1df9364SStefan Roese {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */ 47*f1df9364SStefan Roese {0, 0, 0} 48*f1df9364SStefan Roese }; 49*f1df9364SStefan Roese 50*f1df9364SStefan Roese #else /* CONFIG_CUSTOMER_BOARD_SUPPORT */ 51*f1df9364SStefan Roese 52*f1df9364SStefan Roese struct reg_data ddr3_a38x_933[MV_MAX_DDR3_STATIC_SIZE] = { 53*f1df9364SStefan Roese /* parameters for 933MHZ */ 54*f1df9364SStefan Roese {0x1400, 0x7b00ce3a, 0xffffffff}, 55*f1df9364SStefan Roese {0x1404, 0x36301820, 0xffffffff}, 56*f1df9364SStefan Roese {0x1408, 0x7417eccf, 0xffffffff}, 57*f1df9364SStefan Roese {0x140c, 0x3e421f98, 0xffffffff}, 58*f1df9364SStefan Roese {0x1410, 0x1a300000, 0xffffffff}, 59*f1df9364SStefan Roese {0x1414, 0x00000700, 0xffffffff}, 60*f1df9364SStefan Roese {0x1424, 0x0060f3ff, 0xffffffff}, 61*f1df9364SStefan Roese {0x1428, 0x0013ca50, 0xffffffff}, 62*f1df9364SStefan Roese {0x142c, 0x028c5165, 0xffffffff}, 63*f1df9364SStefan Roese {0x1474, 0x00000000, 0xffffffff}, 64*f1df9364SStefan Roese {0x147c, 0x0000e871, 0xffffffff}, 65*f1df9364SStefan Roese {0x1494, 0x00010000, 0xffffffff}, 66*f1df9364SStefan Roese {0x149c, 0x00000001, 0xffffffff}, 67*f1df9364SStefan Roese {0x14a8, 0x00000000, 0xffffffff}, 68*f1df9364SStefan Roese {0x14cc, 0xbd09000d, 0xffffffff}, 69*f1df9364SStefan Roese {0x1504, 0xffffffe1, 0xffffffff}, 70*f1df9364SStefan Roese {0x150c, 0xffffffe5, 0xffffffff}, 71*f1df9364SStefan Roese {0x1514, 0x00000000, 0xffffffff}, 72*f1df9364SStefan Roese {0x151c, 0x00000000, 0xffffffff}, 73*f1df9364SStefan Roese {0x1538, 0x00000d0d, 0xffffffff}, 74*f1df9364SStefan Roese {0x153c, 0x00000d0d, 0xffffffff}, 75*f1df9364SStefan Roese {0x15d0, 0x00000608, 0xffffffff}, 76*f1df9364SStefan Roese {0x15d4, 0x00000044, 0xffffffff}, 77*f1df9364SStefan Roese {0x15d8, 0x00000020, 0xffffffff}, 78*f1df9364SStefan Roese {0x15dc, 0x00000000, 0xffffffff}, 79*f1df9364SStefan Roese {0x15e0, 0x00000021, 0xffffffff}, 80*f1df9364SStefan Roese {0x15e4, 0x00203c18, 0xffffffff}, 81*f1df9364SStefan Roese {0x15ec, 0xf8000019, 0xffffffff}, 82*f1df9364SStefan Roese {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */ 83*f1df9364SStefan Roese {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */ 84*f1df9364SStefan Roese {0, 0, 0} 85*f1df9364SStefan Roese }; 86*f1df9364SStefan Roese 87*f1df9364SStefan Roese static struct reg_data ddr3_a38x_800[] = { 88*f1df9364SStefan Roese /* parameters for 800MHZ */ 89*f1df9364SStefan Roese {0x1400, 0x7b00cc30, 0xffffffff}, 90*f1df9364SStefan Roese {0x1404, 0x36301820, 0xffffffff}, 91*f1df9364SStefan Roese {0x1408, 0x5415baab, 0xffffffff}, 92*f1df9364SStefan Roese {0x140c, 0x38411def, 0xffffffff}, 93*f1df9364SStefan Roese {0x1410, 0x18300000, 0xffffffff}, 94*f1df9364SStefan Roese {0x1414, 0x00000700, 0xffffffff}, 95*f1df9364SStefan Roese {0x1424, 0x0060f3ff, 0xffffffff}, 96*f1df9364SStefan Roese {0x1428, 0x0011a940, 0xffffffff}, 97*f1df9364SStefan Roese {0x142c, 0x28c5134, 0xffffffff}, 98*f1df9364SStefan Roese {0x1474, 0x00000000, 0xffffffff}, 99*f1df9364SStefan Roese {0x147c, 0x0000d771, 0xffffffff}, 100*f1df9364SStefan Roese {0x1494, 0x00030000, 0xffffffff}, 101*f1df9364SStefan Roese {0x149c, 0x00000300, 0xffffffff}, 102*f1df9364SStefan Roese {0x14a8, 0x00000000, 0xffffffff}, 103*f1df9364SStefan Roese {0x14cc, 0xbd09000d, 0xffffffff}, 104*f1df9364SStefan Roese {0x1504, 0xfffffff1, 0xffffffff}, 105*f1df9364SStefan Roese {0x150c, 0xffffffe5, 0xffffffff}, 106*f1df9364SStefan Roese {0x1514, 0x00000000, 0xffffffff}, 107*f1df9364SStefan Roese {0x151c, 0x00000000, 0xffffffff}, 108*f1df9364SStefan Roese {0x1538, 0x00000b0b, 0xffffffff}, 109*f1df9364SStefan Roese {0x153c, 0x00000c0c, 0xffffffff}, 110*f1df9364SStefan Roese {0x15d0, 0x00000670, 0xffffffff}, 111*f1df9364SStefan Roese {0x15d4, 0x00000046, 0xffffffff}, 112*f1df9364SStefan Roese {0x15d8, 0x00000010, 0xffffffff}, 113*f1df9364SStefan Roese {0x15dc, 0x00000000, 0xffffffff}, 114*f1df9364SStefan Roese {0x15e0, 0x00000023, 0xffffffff}, 115*f1df9364SStefan Roese {0x15e4, 0x00203c18, 0xffffffff}, 116*f1df9364SStefan Roese {0x15ec, 0xf8000019, 0xffffffff}, 117*f1df9364SStefan Roese {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */ 118*f1df9364SStefan Roese {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */ 119*f1df9364SStefan Roese {0, 0, 0} 120*f1df9364SStefan Roese }; 121*f1df9364SStefan Roese 122*f1df9364SStefan Roese static struct reg_data ddr3_a38x_667[] = { 123*f1df9364SStefan Roese /* parameters for 667MHZ */ 124*f1df9364SStefan Roese /* DDR SDRAM Configuration Register */ 125*f1df9364SStefan Roese {0x1400, 0x7b00ca28, 0xffffffff}, 126*f1df9364SStefan Roese /* Dunit Control Low Register - kw28 bit12 low (disable CLK1) */ 127*f1df9364SStefan Roese {0x1404, 0x36301820, 0xffffffff}, 128*f1df9364SStefan Roese /* DDR SDRAM Timing (Low) Register */ 129*f1df9364SStefan Roese {0x1408, 0x43149997, 0xffffffff}, 130*f1df9364SStefan Roese /* DDR SDRAM Timing (High) Register */ 131*f1df9364SStefan Roese {0x140c, 0x38411bc7, 0xffffffff}, 132*f1df9364SStefan Roese /* DDR SDRAM Address Control Register */ 133*f1df9364SStefan Roese {0x1410, 0x14330000, 0xffffffff}, 134*f1df9364SStefan Roese /* DDR SDRAM Open Pages Control Register */ 135*f1df9364SStefan Roese {0x1414, 0x00000700, 0xffffffff}, 136*f1df9364SStefan Roese /* Dunit Control High Register (2 :1 - bits 15:12 = 0xd) */ 137*f1df9364SStefan Roese {0x1424, 0x0060f3ff, 0xffffffff}, 138*f1df9364SStefan Roese /* Dunit Control High Register */ 139*f1df9364SStefan Roese {0x1428, 0x000f8830, 0xffffffff}, 140*f1df9364SStefan Roese /* Dunit Control High Register (2:1 - bit 29 = '1') */ 141*f1df9364SStefan Roese {0x142c, 0x28c50f8, 0xffffffff}, 142*f1df9364SStefan Roese {0x147c, 0x0000c671, 0xffffffff}, 143*f1df9364SStefan Roese /* DDR SDRAM ODT Control (Low) Register */ 144*f1df9364SStefan Roese {0x1494, 0x00030000, 0xffffffff}, 145*f1df9364SStefan Roese /* DDR SDRAM ODT Control (High) Register, will be configured at WL */ 146*f1df9364SStefan Roese {0x1498, 0x00000000, 0xffffffff}, 147*f1df9364SStefan Roese /* DDR Dunit ODT Control Register */ 148*f1df9364SStefan Roese {0x149c, 0x00000300, 0xffffffff}, 149*f1df9364SStefan Roese {0x14a8, 0x00000000, 0xffffffff}, /* */ 150*f1df9364SStefan Roese {0x14cc, 0xbd09000d, 0xffffffff}, /* */ 151*f1df9364SStefan Roese {0x1474, 0x00000000, 0xffffffff}, 152*f1df9364SStefan Roese /* Read Data Sample Delays Register */ 153*f1df9364SStefan Roese {0x1538, 0x00000009, 0xffffffff}, 154*f1df9364SStefan Roese /* Read Data Ready Delay Register */ 155*f1df9364SStefan Roese {0x153c, 0x0000000c, 0xffffffff}, 156*f1df9364SStefan Roese {0x1504, 0xfffffff1, 0xffffffff}, /* */ 157*f1df9364SStefan Roese {0x150c, 0xffffffe5, 0xffffffff}, /* */ 158*f1df9364SStefan Roese {0x1514, 0x00000000, 0xffffffff}, /* */ 159*f1df9364SStefan Roese {0x151c, 0x0, 0xffffffff}, /* */ 160*f1df9364SStefan Roese {0x15d0, 0x00000650, 0xffffffff}, /* MR0 */ 161*f1df9364SStefan Roese {0x15d4, 0x00000046, 0xffffffff}, /* MR1 */ 162*f1df9364SStefan Roese {0x15d8, 0x00000010, 0xffffffff}, /* MR2 */ 163*f1df9364SStefan Roese {0x15dc, 0x00000000, 0xffffffff}, /* MR3 */ 164*f1df9364SStefan Roese {0x15e0, 0x23, 0xffffffff}, /* */ 165*f1df9364SStefan Roese {0x15e4, 0x00203c18, 0xffffffff}, /* ZQC Configuration Register */ 166*f1df9364SStefan Roese {0x15ec, 0xf8000019, 0xffffffff}, /* DDR PHY */ 167*f1df9364SStefan Roese {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */ 168*f1df9364SStefan Roese {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */ 169*f1df9364SStefan Roese {0, 0, 0} 170*f1df9364SStefan Roese }; 171*f1df9364SStefan Roese 172*f1df9364SStefan Roese static struct reg_data ddr3_a38x_533[] = { 173*f1df9364SStefan Roese /* parameters for 533MHZ */ 174*f1df9364SStefan Roese /* DDR SDRAM Configuration Register */ 175*f1df9364SStefan Roese {0x1400, 0x7b00d040, 0xffffffff}, 176*f1df9364SStefan Roese /* Dunit Control Low Register - kw28 bit12 low (disable CLK1) */ 177*f1df9364SStefan Roese {0x1404, 0x36301820, 0xffffffff}, 178*f1df9364SStefan Roese /* DDR SDRAM Timing (Low) Register */ 179*f1df9364SStefan Roese {0x1408, 0x33137772, 0xffffffff}, 180*f1df9364SStefan Roese /* DDR SDRAM Timing (High) Register */ 181*f1df9364SStefan Roese {0x140c, 0x3841199f, 0xffffffff}, 182*f1df9364SStefan Roese /* DDR SDRAM Address Control Register */ 183*f1df9364SStefan Roese {0x1410, 0x10330000, 0xffffffff}, 184*f1df9364SStefan Roese /* DDR SDRAM Open Pages Control Register */ 185*f1df9364SStefan Roese {0x1414, 0x00000700, 0xffffffff}, 186*f1df9364SStefan Roese /* Dunit Control High Register (2 :1 - bits 15:12 = 0xd) */ 187*f1df9364SStefan Roese {0x1424, 0x0060f3ff, 0xffffffff}, 188*f1df9364SStefan Roese /* Dunit Control High Register */ 189*f1df9364SStefan Roese {0x1428, 0x000d6720, 0xffffffff}, 190*f1df9364SStefan Roese /* Dunit Control High Register (2:1 - bit 29 = '1') */ 191*f1df9364SStefan Roese {0x142c, 0x028c50c3, 0xffffffff}, 192*f1df9364SStefan Roese {0x147c, 0x0000b571, 0xffffffff}, 193*f1df9364SStefan Roese /* DDR SDRAM ODT Control (Low) Register */ 194*f1df9364SStefan Roese {0x1494, 0x00030000, 0xffffffff}, 195*f1df9364SStefan Roese /* DDR SDRAM ODT Control (High) Register, will be configured at WL */ 196*f1df9364SStefan Roese {0x1498, 0x00000000, 0xffffffff}, 197*f1df9364SStefan Roese /* DDR Dunit ODT Control Register */ 198*f1df9364SStefan Roese {0x149c, 0x00000003, 0xffffffff}, 199*f1df9364SStefan Roese {0x14a8, 0x00000000, 0xffffffff}, /* */ 200*f1df9364SStefan Roese {0x14cc, 0xbd09000d, 0xffffffff}, /* */ 201*f1df9364SStefan Roese {0x1474, 0x00000000, 0xffffffff}, 202*f1df9364SStefan Roese /* Read Data Sample Delays Register */ 203*f1df9364SStefan Roese {0x1538, 0x00000707, 0xffffffff}, 204*f1df9364SStefan Roese /* Read Data Ready Delay Register */ 205*f1df9364SStefan Roese {0x153c, 0x00000707, 0xffffffff}, 206*f1df9364SStefan Roese {0x1504, 0xffffffe1, 0xffffffff}, /* */ 207*f1df9364SStefan Roese {0x150c, 0xffffffe5, 0xffffffff}, /* */ 208*f1df9364SStefan Roese {0x1514, 0x00000000, 0xffffffff}, /* */ 209*f1df9364SStefan Roese {0x151c, 0x00000000, 0xffffffff}, /* */ 210*f1df9364SStefan Roese {0x15d0, 0x00000630, 0xffffffff}, /* MR0 */ 211*f1df9364SStefan Roese {0x15d4, 0x00000046, 0xffffffff}, /* MR1 */ 212*f1df9364SStefan Roese {0x15d8, 0x00000008, 0xffffffff}, /* MR2 */ 213*f1df9364SStefan Roese {0x15dc, 0x00000000, 0xffffffff}, /* MR3 */ 214*f1df9364SStefan Roese {0x15e0, 0x00000023, 0xffffffff}, /* */ 215*f1df9364SStefan Roese {0x15e4, 0x00203c18, 0xffffffff}, /* ZQC Configuration Register */ 216*f1df9364SStefan Roese {0x15ec, 0xf8000019, 0xffffffff}, /* DDR PHY */ 217*f1df9364SStefan Roese {0x16a0, 0xcc000006, 0xffffffff}, /* Clock Delay */ 218*f1df9364SStefan Roese {0xe4124, 0x08008073, 0xffffffff}, /* AVS BG default */ 219*f1df9364SStefan Roese {0, 0, 0} 220*f1df9364SStefan Roese }; 221*f1df9364SStefan Roese 222*f1df9364SStefan Roese #endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */ 223*f1df9364SStefan Roese 224*f1df9364SStefan Roese #endif /* SUPPORT_STATIC_DUNIT_CONFIG */ 225*f1df9364SStefan Roese 226*f1df9364SStefan Roese #endif /* _DDR3_A38X_MC_STATIC_H */ 227