| /rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/lpc32xx/ |
| H A D | dram.c | 36 writel(0x7FF, &emc->refresh); in ddr_init()
56 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
64 writel((((128) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
67 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
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| /rk3399_rockchip-uboot/drivers/video/ |
| H A D | videomodes.c | 202 GET_OPTION ("refresh:", pPar->refresh) in video_get_params()
298 unsigned int i, xres, yres, depth, refresh; in video_get_ctfb_res_modes() local
304 if (!video_get_video_mode(&xres, &yres, &depth, &refresh, options)) in video_get_ctfb_res_modes()
310 res_mode_init[i].refresh == refresh) { in video_get_ctfb_res_modes()
318 xres, yres, depth, refresh, (*mode_ret)->xres, in video_get_ctfb_res_modes()
319 (*mode_ret)->yres, *depth_ret, (*mode_ret)->refresh); in video_get_ctfb_res_modes()
412 mode->refresh = EDID_DETAILED_TIMING_PIXEL_CLOCK(*t) / in video_edid_dtd_to_ctfb_res_modes()
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| H A D | fsl_diu_fb.c | 24 .refresh = 60,
41 .refresh = 60,
63 .refresh = 60,
79 .refresh = 60,
95 .refresh = 60,
111 .refresh = 60,
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| H A D | fsl_dcu_fb.c | 90 .refresh = 60,
109 .refresh = 60,
125 .refresh = 60,
141 .refresh = 60,
157 .refresh = 60,
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| H A D | videomodes.h | 39 int refresh; /* vertical refresh rate in hz */ member
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| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | rockchip_display_helper.c | 71 int refresh = 0; in drm_mode_vrefresh() local
75 refresh = mode->vrefresh; in drm_mode_vrefresh()
83 refresh = (calc_val + vtotal / 2) / vtotal; in drm_mode_vrefresh()
86 refresh *= 2; in drm_mode_vrefresh()
88 refresh /= 2; in drm_mode_vrefresh()
90 refresh /= mode->vscan; in drm_mode_vrefresh()
92 return refresh; in drm_mode_vrefresh()
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| /rk3399_rockchip-uboot/board/work-microwave/work_92105/ |
| H A D | work_92105_spl.c | 34 .refresh = 128000,
54 .refresh = 128000,
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| /rk3399_rockchip-uboot/board/freescale/mx51evk/ |
| H A D | mx51evk_video.c | 21 .refresh = 57,
37 .refresh = 60,
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| /rk3399_rockchip-uboot/board/boundary/nitrogen6x/ |
| H A D | nitrogen6x.c | 515 .refresh = 60,
535 .refresh = 60,
555 .refresh = 60,
575 .refresh = 60,
595 .refresh = 60,
615 .refresh = 60,
635 .refresh = 60,
655 .refresh = 60,
675 .refresh = 60,
695 .refresh = 57,
[all …]
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| /rk3399_rockchip-uboot/board/freescale/mx53loco/ |
| H A D | mx53loco_video.c | 19 .refresh = 57,
35 .refresh = 60,
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| /rk3399_rockchip-uboot/drivers/video/tegra124/ |
| H A D | display.c | 30 int h_total, v_total, refresh; in tegra_dc_calc_refresh() local
39 refresh = pclk / h_total; in tegra_dc_calc_refresh()
40 refresh *= 1000; in tegra_dc_calc_refresh()
41 refresh /= v_total; in tegra_dc_calc_refresh()
43 return refresh; in tegra_dc_calc_refresh()
48 int refresh = tegra_dc_calc_refresh(timing); in print_mode() local
51 timing->hactive.typ, timing->vactive.typ, refresh / 1000, in print_mode()
52 refresh % 1000, timing->pixelclock.typ); in print_mode()
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3288-dmc.txt | 23 …ck frequency high than sr-enable-freq,this driver should enable the automatic self refresh function
25 …refresh-cnt: Self Refresh idle period. Memories are placed into Self-Refresh mode if the NIF is id…
139 rockchip,auto-self-refresh-cnt = <0>;
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-lpc32xx/ |
| H A D | emc.h | 19 u32 refresh; /* Configures dyn memory refresh operation */ member
95 u32 refresh; member
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| /rk3399_rockchip-uboot/arch/arm/cpu/arm1136/mx35/ |
| H A D | mx35_sdram.c | 41 u32 row, u32 col, u32 dsize, u32 refresh) in mx3_setup_sdram_bank() argument
115 writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh, in mx3_setup_sdram_bank()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx35/ |
| H A D | sys_proto.h | 14 u32 col, u32 dsize, u32 refresh);
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| /rk3399_rockchip-uboot/board/beckhoff/mx53cx9020/ |
| H A D | mx53cx9020_video.c | 22 .refresh = 60,
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| /rk3399_rockchip-uboot/board/timll/devkit3250/ |
| H A D | devkit3250_spl.c | 42 .refresh = 130000, /* 800 clock cycles */
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| /rk3399_rockchip-uboot/include/ |
| H A D | spd.h | 28 unsigned char refresh; /* 12 Refresh Rate/Type */ member
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| /rk3399_rockchip-uboot/board/Seagate/nas220/ |
| H A D | kwbimage.cfg | 28 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
30 # bit24: 1= enable exit self refresh mode on DDR access
37 # bit 5: 0=clk is driven during self refresh, we don't care for APX
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| /rk3399_rockchip-uboot/board/Marvell/guruplug/ |
| H A D | kwbimage.cfg | 25 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
27 # bit24: 1= enable exit self refresh mode on DDR access
34 # bit 5: 0=clk is driven during self refresh, we don't care for APX
|
| /rk3399_rockchip-uboot/board/Seagate/dockstar/ |
| H A D | kwbimage.cfg | 28 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
30 # bit24: 1= enable exit self refresh mode on DDR access
37 # bit 5: 0=clk is driven during self refresh, we don't care for APX
|
| /rk3399_rockchip-uboot/board/Synology/ds109/ |
| H A D | kwbimage.cfg | 29 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
31 # bit24: 1= enable exit self refresh mode on DDR access
38 # bit 5: 0=clk is driven during self refresh, we don't care for APX
|
| /rk3399_rockchip-uboot/board/Marvell/dreamplug/ |
| H A D | kwbimage.cfg | 26 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
28 # bit24: 1= enable exit self refresh mode on DDR access
35 # bit 5: 0=clk is driven during self refresh, we don't care for APX
|
| /rk3399_rockchip-uboot/board/Seagate/goflexhome/ |
| H A D | kwbimage.cfg | 31 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
33 # bit24: 1= enable exit self refresh mode on DDR access
40 # bit 5: 0=clk is driven during self refresh, we don't care for APX
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| /rk3399_rockchip-uboot/board/Marvell/sheevaplug/ |
| H A D | kwbimage.cfg | 25 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
27 # bit24: 1= enable exit self refresh mode on DDR access
34 # bit 5: 0=clk is driven during self refresh, we don't care for APX
|