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Searched refs:r5 (Results 1 – 25 of 82) sorted by relevance

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/rk3399_rockchip-uboot/arch/powerpc/lib/
H A Dppcstring.S13 addi r5,r3,-1
17 stbu r0,1(r5)
23 cmpwi 0,r5,0
25 mtctr r5
36 addi r5,r3,-1
38 1: lbzu r0,1(r5)
41 addi r5,r5,-1
44 stbu r0,1(r5)
50 addi r5,r3,-1
52 1: lbzu r3,1(r5)
[all …]
H A Dppccache.S69 li r5,L1_CACHE_BYTES-1
70 andc r3,r3,r5
72 add r4,r4,r5
93 li r5,L1_CACHE_BYTES-1
94 andc r3,r3,r5
96 add r4,r4,r5
/rk3399_rockchip-uboot/arch/nios2/cpu/
H A Dstart.S35 movhi r5, %hi(ICACHE_SIZE_MAX)
36 ori r5, r5, %lo(ICACHE_SIZE_MAX)
37 0: initi r5
38 sub r5, r5, r4
39 bgt r5, r0, 0b
64 movhi r5, %hi(DCACHE_SIZE_MAX)
65 ori r5, r5, %lo(DCACHE_SIZE_MAX)
69 bltu r6, r5, 1b
78 _cur: movhi r5, %hi(_cur - _start)
79 ori r5, r5, %lo(_cur - _start)
[all …]
/rk3399_rockchip-uboot/arch/sh/lib/
H A Dudivsi3_i4i-Os.S29 extu.w r5,r0
30 cmp/eq r5,r0
35 mov.l r5,@-r15
36 shll16 r5
38 div1 r5,r4
40 div1 r5,r4
41 div1 r5,r4
43 div1 r5,r4
48 div1 r5,r4
50 div1 r5,r4
[all …]
H A Dudivsi3.S16 div1 r5,r4
18 div1 r5,r4; div1 r5,r4; div1 r5,r4
19 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
22 div1 r5,r4; rotcl r0
23 div1 r5,r4; rotcl r0
24 div1 r5,r4; rotcl r0
25 rts; div1 r5,r4
29 extu.w r5,r0
30 cmp/eq r5,r0
36 shll16 r5
[all …]
H A Dudivsi3_i4i.S46 cmp/hi r1,r5
47 extu.w r5,r1
49 cmp/eq r5,r1
52 mov r5,r1
53 shll16 r5
55 div1 r5,r0
57 div1 r5,r0
58 div1 r5,r0
60 div1 r5,r0
65 mov.b @(r0,r5),r1
[all …]
H A Dmovmem.S31 mov.l @(48,r5),r0
34 mov.l @(60,r5),r0
38 mov.l @(56,r5),r0
42 mov.l @(52,r5),r0
43 add #64,r5
55 mov.l @(52,r5),r0
64 mov.l @(60,r5),r0
70 mov.l @(56,r5),r0
76 mov.l @(52,r5),r0
82 mov.l @(48,r5),r0
[all …]
/rk3399_rockchip-uboot/arch/arc/lib/
H A Dstart.S19 lr r5, [identity]
20 lsr r5, r5, 8
21 bmsk r5, r5, 7
22 cmp r5, 0
23 mov.nz r0, r5
37 lr r5, [ARC_BCR_IC_BUILD]
38 breq r5, 0, 1f ; I$ doesn't exist
51 lr r5, [ARC_AUX_DC_CTRL]
52 bclr r5, r5, 6 ; Invalidate (discard w/o wback)
54 bclr r5, r5, 0 ; Enable (+Inv)
[all …]
H A Dmemcmp.S23 ld %r5, [%r1, 0]
28 brne %r4, %r5, .Leven
30 ld.a %r5, [%r1, 8]
36 brne %r4, %r5, .Leven
38 ld %r5, [%r1, 4]
43 xor %r0, %r4, %r5
51 xor %r0, %r4, %r5
59 asl %r12, %r5, %r1
82 lsr %r5, %r5, SHIFT
85 sub.f %r0, %r4, %r5
[all …]
H A Dmemcpy-700.S12 mov_s %r5, %r0
19 st.ab %r12, [%r5, 4]
24 st.ab %r12, [%r5, 4]
26 st.ab %r3, [%r5, 4]
29 ld %r3, [%r5, 0]
45 st %r12, [%r5, 0]
53 stb.ab %r12, [%r5, 1]
58 stb.ab %r12, [%r5, 1]
60 stb.ab %r3, [%r5, 1]
63 stb %r12, [%r5, 0]
/rk3399_rockchip-uboot/arch/nds32/include/asm/
H A Dmacro.h27 li $r5, \data
28 swi $r5, [$r4]
33 li $r5, \data
34 shi $r5, [$r4]
39 li $r5, \data
40 sbi $r5, [$r4]
50 lwi $r5, [$r4]
52 or $r5, $r5, $r6
53 swi $r5, [$r4]
58 lwi $r5, [$r4]
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dpsci.S42 mrc p15, 0, r5, c1, c1, 0 @ Read SCR
43 bic r5, r5, #1 @ Secure mode
44 mcr p15, 0, r5, c1, c1, 0 @ Write SCR
49 ldr r5, [r4]
50 orr r5, r5, #NS_RST_VEC_WR_DIS
51 str r5, [r4]
55 adr r5, _sys_clock_freq
59 streq r7, [r5]
61 ldrne r7, [r5]
78 mov r5, #(CSR_ENABLE)
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc86xx/
H A Dcache.S57 lis r5,CACHE_LINE_SIZE
59 cmp 0,1,r3,r5
61 lwz r5,0(r3)
62 lis r5,CACHE_LINE_SIZE
75 li r5,CACHE_LINE_SIZE-1
76 andc r3,r3,r5
78 add r4,r4,r5
102 li r5,CACHE_LINE_SIZE-1
103 andc r3,r3,r5 /* align r3 down to cache line */
105 add r4,r4,r5 /* r4 += cache_line_size-1 */
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dsleep.S29 mov r5, sp
37 mov r1, r5
59 ubfx r5, r4, #4, #12
62 cmp r5, r4
66 cmp r5, r4
74 read_diag r5
75 stmia r0!, {r4 - r5}
79 read_tpidruro r5
80 stmia r0!, {r4 - r5}
84 read_ttbr0 r5
[all …]
H A Dnonsec_virt.S48 ldr r5, =_psci_vectors @ Switch to the next monitor
49 mcr p15, 0, r5, c12, c0, 1
62 mrc p15, 0, r5, c1, c0, 1
63 orr r5, r5, #(1 << 1)
64 mcr p15, 0, r5, c1, c0, 1
69 mrc p15, 0, r5, c1, c0, 1
70 orr r5, r5, #(1 << 25)
71 mcr p15, 0, r5, c1, c0, 1
75 mrc p15, 0, r5, c1, c1, 0 @ read SCR
76 bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
[all …]
/rk3399_rockchip-uboot/board/nokia/rx51/
H A Dlowlevel_init.S72 mov r5, #0
73 str r5, [r3]
77 ldr r5, ih_magic /* r5 - IH_MAGIC */
78 cmp r4, r5
88 mov r5, #0
89 str r5, [r0] /* remove 4 bytes header of kernel */
102 subhi r5, r0, r1
103 sublo r5, r1, r0
112 addhi r0, r1, r5
113 sublo r0, r1, r5
[all …]
/rk3399_rockchip-uboot/arch/nds32/cpu/n1213/ag101/
H A Dlowlevel_init.S201 li $r5, 0x0
202 swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
203 swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
236 li $r5, AHBC_BSR6_A
237 lwi $r8, [$r5]
241 la $r5, _start@GOTOFF
244 lwi.p $r7, [$r5], #4
246 blt $r5, $r6, 1b
258 li $r5, CONFIG_SYS_TEXT_BASE /* flash base address */
259 add $r11, $r11, $r5 /* add flash address offset for ret */
[all …]
/rk3399_rockchip-uboot/post/lib_powerpc/
H A Dasm.S28 mr r4, r5
51 mr r4, r5
52 mr r5, r6
73 mr r3, r5
94 mr r3, r5
112 stwu r5, -4(r1)
142 stwu r5, -4(r1)
175 mr r4, r5
176 mr r5, r6
197 mr r4, r5
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx7/
H A Dmx7_plugin.S72 push {r5}
73 ldr r5, boot_data2
74 str r5, [r0]
75 ldr r5, image_len2
76 str r5, [r1]
77 ldr r5, second_ivt_offset
78 str r5, [r2]
80 pop {r5}
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap3/
H A Dlowlevel_init.S77 ldr r5, [r3] /* get status */
78 and r5, r5, #0x1 /* isolate core status */
79 cmp r5, #0x1 /* still locked? */
83 ldr r5, pll_div_add1
84 str r1, [r5] /* set m, n, m2 */
85 ldr r5, pll_div_add2
86 str r2, [r5] /* set l3/l4/.. dividers*/
87 ldr r5, pll_div_add3 /* wkup */
89 str r2, [r5]
90 ldr r5, pll_div_add4 /* gfx */
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap5/
H A Dsec_entry_cpu1.S65 mov r5, #0x0
66 str r5, [r4]
80 push {r4, r5, lr}
90 ldr r5, =cpu1_entry
91 str r5, [r4] @ Setup CPU1 entry function
93 mov r5, #0x10
94 str r5, [r4] @ Tell ROM to exit while loop
99 ldr r5, [r4] @ Check if CPU1 is done
100 cmp r5, #0
105 pop {r4, r5, pc}
/rk3399_rockchip-uboot/drivers/rkflash/
H A Drk_sftl_arm_v7.S29 push {r3, r4, r5, r6, r7, r8, r10, lr}
39 ldrh r5, [r3, #10]
44 lsleq r5, r5, #1
47 uxtheq r5, r5
51 mla r4, r5, r4, r6
55 pop {r3, r4, r5, r6, r7, r8, r10, pc}
158 push {r0, r1, r4, r5, r6, r7, r8, r10, fp, lr}
162 ldrh r5, [r0, #2]
169 strh r5, [r2] @ movhi
200 smulbb r5, r5, r0
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/
H A Dstart.S101 mfmsr r5
102 ori r5, r5, (MSR_IR | MSR_DR)
103 mtmsr r5
168 mfmsr r5 /* save msr contents */
212 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
213 mtlr r5
332 mfspr r5,DSISR
333 stw r5,_DSISR(r21)
492 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
494 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
[all …]
/rk3399_rockchip-uboot/drivers/rknand/
H A Drk_ftl_arm_v7.S102 push {r4, r5, lr}
115 pop {r4, r5, pc}
117 ldrb r5, [r0, r3] @ zero_extendqisi2
120 cmp r5, r4
123 pop {r4, r5, pc}
202 push {r3, r4, r5, lr}
205 mov r5, r0
215 ldr r3, [r3, r5, lsl #3]
217 pop {r3, r4, r5, pc}
275 push {r4, r5}
[all …]
H A Drk_zftl_arm_v7.S32 push {r4, r5, lr}
37 pop {r4, r5, pc}
39 ldrb r5, [r0, r3] @ zero_extendqisi2
42 cmp r5, r4
45 pop {r4, r5, pc}
59 push {r3, r4, r5, r6, r7, lr}
70 ldrh r5, [r3]
71 mov r1, r5
73 mov r1, r5
74 mul r6, r5, r0
[all …]

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