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Searched refs:parent_rate (Results 1 – 12 of 12) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_cru.c61 unsigned long parent_rate = REFCLK_RATE; in rk628_cru_clk_get_rate_pll() local
75 return parent_rate; in rk628_cru_clk_get_rate_pll()
82 return parent_rate; in rk628_cru_clk_get_rate_pll()
89 return parent_rate; in rk628_cru_clk_get_rate_pll()
107 return parent_rate; in rk628_cru_clk_get_rate_pll()
109 foutvco = parent_rate * fbdiv; in rk628_cru_clk_get_rate_pll()
113 u64 frac_rate = (u64)parent_rate * frac; in rk628_cru_clk_get_rate_pll()
277 unsigned long m, n, parent_rate; in rk628_cru_clk_set_rate_sclk_vop() local
284 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_GPLL); in rk628_cru_clk_set_rate_sclk_vop()
286 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_CPLL); in rk628_cru_clk_set_rate_sclk_vop()
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/rk3399_rockchip-uboot/drivers/clk/
H A Dclk_pic32.c171 int parent_rate, int rate, int parent_id) in pic32_set_refclk() argument
182 if (parent_rate <= rate) { in pic32_set_refclk()
186 div = parent_rate / (rate << 1); in pic32_set_refclk()
187 frac = parent_rate; in pic32_set_refclk()
232 u32 rodiv, rotrim, rosel, v, parent_rate; in pic32_get_refclk() local
255 parent_rate = pic32_get_cpuclk(priv); in pic32_get_refclk()
258 parent_rate = pic32_get_pll_rate(priv); in pic32_get_refclk()
261 parent_rate = 0; in pic32_get_refclk()
271 rate64 = parent_rate; in pic32_get_refclk()
276 v = parent_rate / (rodiv << 1); in pic32_get_refclk()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dclock.c246 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate, in clk_get_divider() argument
249 u64 divider = parent_rate * 2; in clk_get_divider()
300 static unsigned long get_rate_from_divider(unsigned long parent_rate, in get_rate_from_divider() argument
305 rate = (u64)parent_rate * 2; in get_rate_from_divider()
314 unsigned parent_rate = pll_rate[parent]; in clock_get_periph_rate() local
325 return parent_rate; in clock_get_periph_rate()
353 return get_rate_from_divider(parent_rate, div); in clock_get_periph_rate()
369 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate, in find_best_divider() argument
378 unsigned divided_parent = parent_rate >> shift; in find_best_divider()
528 unsigned int __weak clk_m_get_rate(unsigned int parent_rate) in clk_m_get_rate() argument
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/rk3399_rockchip-uboot/drivers/clk/at91/
H A Dclk-generated.c82 ulong tmp_rate, best_rate = rate, parent_rate; in generic_clk_set_rate() local
95 parent_rate = clk_get_rate(&parent); in generic_clk_set_rate()
96 if (IS_ERR_VALUE(parent_rate)) in generic_clk_set_rate()
97 return parent_rate; in generic_clk_set_rate()
100 tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div); in generic_clk_set_rate()
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rv1108.c306 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_bus_get_clk() local
312 return DIV_TO_RATE(parent_rate, div); in rv1108_aclk_bus_get_clk()
318 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_bus_set_clk() local
320 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_aclk_bus_set_clk()
334 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_peri_get_clk() local
340 return DIV_TO_RATE(parent_rate, div); in rv1108_aclk_peri_get_clk()
346 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_hclk_peri_get_clk() local
352 return DIV_TO_RATE(parent_rate, div); in rv1108_hclk_peri_get_clk()
358 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_pclk_peri_get_clk() local
364 return DIV_TO_RATE(parent_rate, div); in rv1108_pclk_peri_get_clk()
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H A Dclk_rk3288.c867 ulong rate, parent_rate; in rockchip_aclk_peri_get_clk() local
873 parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rockchip_aclk_peri_get_clk()
875 parent_rate = rkclk_pll_get_rate(cru, CLK_CODEC); in rockchip_aclk_peri_get_clk()
876 rate = DIV_TO_RATE(parent_rate, div); in rockchip_aclk_peri_get_clk()
885 ulong rate, parent_rate; in rockchip_aclk_cpu_get_clk() local
891 parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rockchip_aclk_cpu_get_clk()
893 parent_rate = rkclk_pll_get_rate(cru, CLK_CODEC); in rockchip_aclk_cpu_get_clk()
894 parent_rate = DIV_TO_RATE(parent_rate, div); in rockchip_aclk_cpu_get_clk()
897 rate = DIV_TO_RATE(parent_rate, div); in rockchip_aclk_cpu_get_clk()
906 ulong rate, parent_rate; in rockchip_pclk_peri_get_clk() local
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H A Dclk_rk3368.c357 ulong parent_rate = parents[i].rate; in rk3368_mmc_find_best_rate_and_parent() local
358 u32 div = DIV_ROUND_UP(parent_rate, rate); in rk3368_mmc_find_best_rate_and_parent()
360 ulong new_rate = parent_rate / adj_div; in rk3368_mmc_find_best_rate_and_parent()
/rk3399_rockchip-uboot/drivers/video/
H A Dipu_common.c298 u64 parent_rate = (unsigned long long)clk->parent->rate * 16; in ipu_pixel_clk_round_rate() local
305 div = parent_rate; in ipu_pixel_clk_round_rate()
321 final_rate = parent_rate; in ipu_pixel_clk_round_rate()
329 u64 div, parent_rate; in ipu_pixel_clk_set_rate() local
332 parent_rate = (unsigned long long)clk->parent->rate * 16; in ipu_pixel_clk_set_rate()
333 div = parent_rate; in ipu_pixel_clk_set_rate()
355 do_div(parent_rate, div); in ipu_pixel_clk_set_rate()
357 clk->rate = parent_rate; in ipu_pixel_clk_set_rate()
/rk3399_rockchip-uboot/drivers/video/drm/
H A Drockchip-inno-hdmi-phy.c208 unsigned long parent_rate);
889 unsigned long parent_rate) in inno_hdmi_3328_phy_pll_recalc_rate() argument
898 vco = parent_rate * nf; in inno_hdmi_3328_phy_pll_recalc_rate()
903 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); in inno_hdmi_3328_phy_pll_recalc_rate()
1099 unsigned long parent_rate) in inno_hdmi_rk3528_phy_pll_recalc_rate() argument
1104 u64 vco = parent_rate; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1113 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); in inno_hdmi_rk3528_phy_pll_recalc_rate()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra/
H A Dclock.h48 unsigned int clk_m_get_rate(unsigned int parent_rate);
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx5/
H A Dclock.c725 u32 parent_rate = get_emi_slow_clk(); in config_nfc_clk() local
730 div = parent_rate / nfc_clk; in config_nfc_clk()
733 if (parent_rate / div > NFC_CLK_MAX) in config_nfc_clk()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1034 unsigned int clk_m_get_rate(unsigned parent_rate) in clk_m_get_rate() argument
1042 return parent_rate / div; in clk_m_get_rate()