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Searched refs:mtspr (Results 1 – 19 of 19) sorted by relevance

/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc86xx/
H A Drelease.S34 mtspr PIR, r0
38 mtspr IBAT0U, r0
39 mtspr IBAT1U, r0
40 mtspr IBAT2U, r0
41 mtspr IBAT3U, r0
42 mtspr IBAT4U, r0
43 mtspr IBAT5U, r0
44 mtspr IBAT6U, r0
45 mtspr IBAT7U, r0
47 mtspr DBAT0U, r0
[all …]
H A Dstart.S146 mtspr HID0, r0
162 mtspr l2cr, r3
202 mtspr SPRN_SRR0,r3
203 mtspr SPRN_SRR1,r5
287 mtspr IBAT0U, r0
288 mtspr IBAT1U, r0
289 mtspr IBAT2U, r0
290 mtspr IBAT3U, r0
291 mtspr IBAT4U, r0
292 mtspr IBAT5U, r0
[all …]
H A Dcache.S38 mtspr HID0,r3
48 mtspr HID0,r3
180 mtspr HID0, r5
181 mtspr HID0, r3
197 mtspr HID0, r3
214 mtspr HID0, r3 /* no invalidate, unlock */
217 mtspr HID0, r5 /* enable + invalidate */
218 mtspr HID0, r3 /* enable */
230 mtspr HID0, r3 /* no invalidate, unlock */
233 mtspr HID0, r5 /* enable + invalidate */
[all …]
/rk3399_rockchip-uboot/arch/powerpc/lib/
H A Dbat_rw.c28 mtspr (DBAT0L, lower); in write_bat()
29 mtspr (DBAT0U, upper); in write_bat()
33 mtspr (IBAT0L, lower); in write_bat()
34 mtspr (IBAT0U, upper); in write_bat()
37 mtspr (DBAT1L, lower); in write_bat()
38 mtspr (DBAT1U, upper); in write_bat()
42 mtspr (IBAT1L, lower); in write_bat()
43 mtspr (IBAT1U, upper); in write_bat()
46 mtspr (DBAT2L, lower); in write_bat()
47 mtspr (DBAT2U, upper); in write_bat()
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc8xx/
H A Dcache.c22 mtspr(IC_CST, IDC_INVALL); in icache_enable()
23 mtspr(IC_CST, IDC_ENABLE); in icache_enable()
29 mtspr(IC_CST, IDC_DISABLE); in icache_disable()
39 mtspr(MD_CTR, MD_RESETVAL); /* Set cache mode with MMU off */ in dcache_enable()
40 mtspr(DC_CST, IDC_INVALL); in dcache_enable()
41 mtspr(DC_CST, IDC_ENABLE); in dcache_enable()
47 mtspr(DC_CST, IDC_DISABLE); in dcache_disable()
48 mtspr(DC_CST, IDC_INVALL); in dcache_disable()
H A Dstart.S74 mtspr 638, r3
80 mtspr SRR1, r3 /* Make SRR1 match MSR */
87 mtspr LCTRL1, r0 /* Initialize debug port regs */
88 mtspr LCTRL2, r0
89 mtspr COUNTA, r0
90 mtspr COUNTB, r0
99 mtspr IC_CST, r3
100 mtspr DC_CST, r3
103 mtspr IC_CST, r3
104 mtspr DC_CST, r3
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S38 mtspr SPRN_HID0,r3
49 mtspr SPRN_HID1,r3
55 mtspr SPRN_HDBCR1,r3
80 mtspr SPRN_HDBCR0,r3
88 mtspr SPRN_BUCSR,r3
98 mtspr SPRN_L1CSR1,r2
106 mtspr SPRN_L1CSR1,r3
116 mtspr SPRN_L1CSR0,r2
124 mtspr SPRN_L1CSR0,r3
185 mtspr SPRN_PIR,r4 /* write to PIR register */
[all …]
H A Dstart.S114 mtspr SPRN_HDBCR0,r3
123 mtspr SPRN_HDBCR0, r3
148 mtspr SPRN_L2CSR0,r3
161 mtspr SPRN_L2CSR0,r4
171 mtspr L1CSR0,r0 /* invalidate d-cache */
172 mtspr L1CSR1,r0 /* invalidate i-cache */
175 mtspr DBSR,r1 /* Clear all valid bits */
181 mtspr MAS0, \scratch
184 mtspr MAS1, \scratch
187 mtspr MAS2, \scratch
[all …]
H A Dcpu_init_early.c35 mtspr(MAS0, _mas0); in setup_ifc()
36 mtspr(MAS1, _mas1); in setup_ifc()
37 mtspr(MAS2, _mas2); in setup_ifc()
38 mtspr(MAS3, _mas3); in setup_ifc()
39 mtspr(MAS7, _mas7); in setup_ifc()
63 mtspr(MAS0, _mas0); in setup_ifc()
64 mtspr(MAS1, _mas1); in setup_ifc()
65 mtspr(MAS2, _mas2); in setup_ifc()
66 mtspr(MAS3, _mas3); in setup_ifc()
67 mtspr(MAS7, _mas7); in setup_ifc()
H A Dtlb.c24 mtspr(MMUCSR0, 0x4); in invalidate_tlb()
26 mtspr(MMUCSR0, 0x2); in invalidate_tlb()
51 mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0)); in read_tlbcam_entry()
110 mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); in init_used_tlb_cams()
178 mtspr(MAS0, _mas0); in disable_tlb()
179 mtspr(MAS1, _mas1); in disable_tlb()
180 mtspr(MAS2, _mas2); in disable_tlb()
181 mtspr(MAS3, _mas3); in disable_tlb()
183 mtspr(MAS7, 0); in disable_tlb()
204 mtspr(MAS6, 0); in find_tlb_idx()
H A Dinterrupts.c45 mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE); in interrupt_init_cpu()
99 mtspr(SPRN_TSR, TSR_PIS); in timer_interrupt_cpu()
H A Dmp.c312 mtspr(SPRN_TBWU, 0); in plat_mp_up()
313 mtspr(SPRN_TBWL, 0); in plat_mp_up()
388 mtspr(SPRN_TBWU, 0); in plat_mp_up()
389 mtspr(SPRN_TBWL, 0); in plat_mp_up()
H A Dcpu_init.c686 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); in l2cache_init()
692 mtspr(SPRN_L2CSR1, (32 + 1)); in l2cache_init()
696 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); in l2cache_init()
776 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); in cpu_init_r()
783 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); in cpu_init_r()
793 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); in cpu_init_r()
H A Dcpu.c311 mtspr(DBCR0,val); in do_reset()
346 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) | in init_85xx_watchdog()
356 mtspr(SPRN_TSR, TSR_WIS); in reset_85xx_watchdog()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/
H A Dstart.S115 mtspr SRR0, r4
116 mtspr SRR1, r3
444 mtspr SRR0,r24
445 mtspr SRR1,r20
464 mtspr XER,r2
472 mtspr SRR0,r2
473 mtspr SRR1,r0
499 mtspr SRR1, r3 /* Make SRR1 match MSR */
548 mtspr HID0, r3
553 mtspr HID0, r3
[all …]
/rk3399_rockchip-uboot/arch/powerpc/include/asm/
H A Dcache.h119 mtspr(IC_CST, val); in wr_ic_cst()
124 mtspr(IC_ADR, val); in wr_ic_adr()
134 mtspr(DC_CST, val); in wr_dc_cst()
139 mtspr(DC_ADR, val); in wr_dc_adr()
H A Dprocessor.h1154 #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) macro
/rk3399_rockchip-uboot/include/
H A Dppc_asm.tmpl166 mtspr SPRG0,r20; \
167 mtspr SPRG1,r21; \
/rk3399_rockchip-uboot/doc/
H A DREADME.POST438 loading a fixed value into the XER register (mtspr), moving XER