| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | analogix_dp.c | 192 int lane, lane_count, retval; in analogix_dp_link_start() local
194 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
199 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
204 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start()
208 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, dp->link_train.lane_count); in analogix_dp_link_start()
213 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start()
241 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
256 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
261 lane_count); in analogix_dp_link_start()
276 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in analogix_dp_clock_recovery_ok() argument
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| H A D | drm_dp_helper.c | 53 int lane_count) in drm_dp_channel_eq_ok() argument
63 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
72 int lane_count) in drm_dp_clock_recovery_ok() argument
77 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
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| H A D | analogix_dp_reg.c | 723 phy_cfg.dp.lanes = dp->link_train.lane_count; in analogix_dp_set_link_bandwidth()
763 phy_cfg.dp.lanes = dp->link_train.lane_count; in analogix_dp_set_lane_count()
789 for (lane = 0; lane < dp->link_train.lane_count; lane++) { in analogix_dp_set_lane_link_training()
805 phy_cfg.dp.lanes = dp->link_train.lane_count; in analogix_dp_set_lane_link_training()
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| H A D | analogix_dp.h | 614 u8 lane_count; member
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| /rk3399_rockchip-uboot/drivers/video/tegra124/ |
| H A D | dp.c | 434 link_cfg->lane_count); in tegra_dc_dp_dump_link_cfg()
459 cfg->lane_count /= 2; in _tegra_dp_lower_link_config()
465 if (cfg->lane_count == 1) { in _tegra_dp_lower_link_config()
467 cfg->lane_count = cfg->max_lane_count; in _tegra_dp_lower_link_config()
469 cfg->lane_count /= 2; in _tegra_dp_lower_link_config()
477 return (cfg->lane_count > 0) ? 0 : -ENOLINK; in _tegra_dp_lower_link_config()
510 if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ || in tegra_dc_dp_calc_config()
515 (u64)link_rate * 8 * link_cfg->lane_count) in tegra_dc_dp_calc_config()
523 do_div(ratio_f, link_rate * link_cfg->lane_count); in tegra_dc_dp_calc_config()
603 (8 * link_cfg->lane_count); in tegra_dc_dp_calc_config()
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| H A D | sor.c | 215 u32 lane_count, int pu) in tegra_dc_sor_power_dplanes() argument
223 switch (lane_count) { in tegra_dc_sor_power_dplanes()
234 debug("dp: invalid lane number %d\n", lane_count); in tegra_dc_sor_power_dplanes()
239 tegra_dc_sor_set_lane_count(dev, lane_count); in tegra_dc_sor_power_dplanes()
390 u8 *lane_count) in tegra_dc_sor_read_link_config() argument
403 *lane_count = 0; in tegra_dc_sor_read_link_config()
406 *lane_count = 1; in tegra_dc_sor_read_link_config()
409 *lane_count = 2; in tegra_dc_sor_read_link_config()
412 *lane_count = 4; in tegra_dc_sor_read_link_config()
428 void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count) in tegra_dc_sor_set_lane_count() argument
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| H A D | sor.h | 855 u8 lane_count; member
885 void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count);
890 u8 *lane_count);
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| /rk3399_rockchip-uboot/drivers/video/rockchip/ |
| H A D | rk_edp.c | 329 values[1] = edp->link_train.lane_count; in rk_edp_link_configure()
340 for (i = 0; i < edp->link_train.lane_count; i++) in rk_edp_set_link_training()
365 static int rk_edp_clock_recovery(const u8 *link_status, int lane_count) in rk_edp_clock_recovery() argument
370 for (lane = 0; lane < lane_count; lane++) { in rk_edp_clock_recovery()
379 static int rk_edp_channel_eq(const u8 *link_status, int lane_count) in rk_edp_channel_eq() argument
389 for (lane = 0; lane < lane_count; lane++) { in rk_edp_channel_eq()
421 static void edp_get_adjust_train(const u8 *link_status, int lane_count, in edp_get_adjust_train() argument
428 for (lane = 0; lane < lane_count; lane++) { in edp_get_adjust_train()
487 edp->link_train.lane_count); in rk_edp_link_train_cr()
500 edp->link_train.lane_count); in rk_edp_link_train_cr()
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| /rk3399_rockchip-uboot/drivers/video/drm/display-serdes/ |
| H A D | core.h | 259 u32 lane_count; member
274 u32 lane_count; member
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| /rk3399_rockchip-uboot/drivers/video/drm/display-serdes/maxim/ |
| H A D | maxim-max96772.c | 331 serdes_reg_write(serdes, 0xe792, serdes->serdes_panel->lane_count); in max96772_panel_prepare()
391 hwords = DIV_ROUND_UP(hact * 24, 16) - serdes->serdes_panel->lane_count; in max96772_panel_prepare()
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| /rk3399_rockchip-uboot/include/drm/ |
| H A D | drm_dp_helper.h | 1006 int lane_count);
1008 int lane_count);
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | edp_rk3288.h | 633 u8 lane_count; member
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