192 	int lane, lane_count, retval;  in analogix_dp_link_start()  local
194 	lane_count = dp->link_train.lane_count;  in analogix_dp_link_start()
199 	for (lane = 0; lane < lane_count; lane++)  in analogix_dp_link_start()
204 	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);  in analogix_dp_link_start()
208 		drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, dp->link_train.lane_count);  in analogix_dp_link_start()
213 		buf[1] = dp->link_train.lane_count;  in analogix_dp_link_start()
241 	for (lane = 0; lane < lane_count; lane++)  in analogix_dp_link_start()
256 	for (lane = 0; lane < lane_count; lane++)  in analogix_dp_link_start()
261 				   lane_count);  in analogix_dp_link_start()
276 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)  in analogix_dp_clock_recovery_ok()  argument
281 	for (lane = 0; lane < lane_count; lane++) {  in analogix_dp_clock_recovery_ok()
290 				     int lane_count)  in analogix_dp_channel_eq_ok()  argument
298 	for (lane = 0; lane < lane_count; lane++) {  in analogix_dp_channel_eq_ok()
338 	int lane, lane_count;  in analogix_dp_get_adjust_training_lane()  local
341 	lane_count = dp->link_train.lane_count;  in analogix_dp_get_adjust_training_lane()
342 	for (lane = 0; lane < lane_count; lane++) {  in analogix_dp_get_adjust_training_lane()
374 	int lane, lane_count, retval;  in analogix_dp_process_clock_recovery()  local
381 	lane_count = dp->link_train.lane_count;  in analogix_dp_process_clock_recovery()
387 	if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {  in analogix_dp_process_clock_recovery()
411 		for (lane = 0; lane < lane_count; lane++) {  in analogix_dp_process_clock_recovery()
447 				   dp->link_train.training_lane, lane_count);  in analogix_dp_process_clock_recovery()
456 	int lane_count, retval;  in analogix_dp_process_equalizer_training()  local
462 	lane_count = dp->link_train.lane_count;  in analogix_dp_process_equalizer_training()
468 	if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {  in analogix_dp_process_equalizer_training()
477 	if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {  in analogix_dp_process_equalizer_training()
488 		dp->link_train.lane_count = reg;  in analogix_dp_process_equalizer_training()
491 		       dp->link_train.link_rate, dp->link_train.lane_count);  in analogix_dp_process_equalizer_training()
515 				   dp->link_train.training_lane, lane_count);  in analogix_dp_process_equalizer_training()
536 static bool analogix_dp_link_config_validate(u8 link_rate, u8 lane_count)  in analogix_dp_link_config_validate()  argument
552 	switch (lane_count) {  in analogix_dp_link_config_validate()
575 					      dp->link_rate_table[i], dp->link_train.lane_count))  in analogix_dp_select_link_rate_from_table()
579 		    analogix_dp_link_config_validate(bw_code, dp->link_train.lane_count)) {  in analogix_dp_select_link_rate_from_table()
673 					      u8 *lane_count)  in analogix_dp_get_max_rx_lane_count()  argument
686 	*lane_count = DPCD_MAX_LANE_COUNT(data);  in analogix_dp_get_max_rx_lane_count()
704 	dp->link_train.lane_count = min_t(u32, dp->link_train.lane_count, max_lane);  in analogix_dp_init_training()
1013 					      dp->link_train.lane_count))  in analogix_dp_get_output_format_by_edid()
1160 		ret = analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);  in analogix_dp_connector_detect()
1203 	max_lane_count = min_t(u32, dp->video_info.max_lane_count, dp->link_train.lane_count);  in analogix_dp_mode_valid()