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Searched refs:in_be32 (Results 1 – 25 of 225) sorted by relevance

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/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc8xx/
H A Dreginfo.c27 printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr)); in print_reginfo()
28 printf("\tSYPCR\t0x%08X\n", in_be32(&sysconf->sc_sypcr)); in print_reginfo()
30 printf("\tSWT\t0x%08X", in_be32(&sysconf->sc_swt)); in print_reginfo()
34 in_be32(&sysconf->sc_sipend), in_be32(&sysconf->sc_simask)); in print_reginfo()
36 in_be32(&sysconf->sc_siel), in_be32(&sysconf->sc_sivec)); in print_reginfo()
38 in_be32(&sysconf->sc_tesr), in_be32(&sysconf->sc_sdcr)); in print_reginfo()
41 printf("\tBR0\t0x%08X\tOR0\t0x%08X\n", in_be32(&memctl->memc_br0), in print_reginfo()
42 in_be32(&memctl->memc_or0)); in print_reginfo()
43 printf("\tBR1\t0x%08X\tOR1\t0x%08X\n", in_be32(&memctl->memc_br1), in print_reginfo()
44 in_be32(&memctl->memc_or1)); in print_reginfo()
[all …]
H A Dimmap.c28 in_be32(&sc->sc_siumcr), in_be32(&sc->sc_sypcr)); in do_siuinfo()
29 printf("SWT = %08x\n", in_be32(&sc->sc_swt)); in do_siuinfo()
31 in_be32(&sc->sc_sipend), in_be32(&sc->sc_simask)); in do_siuinfo()
33 in_be32(&sc->sc_siel), in_be32(&sc->sc_sivec)); in do_siuinfo()
35 in_be32(&sc->sc_tesr), in_be32(&sc->sc_sdcr)); in do_siuinfo()
50 i, in_be32(p), i, in_be32(p + 1)); in do_memcinfo()
52 printf("MAR = %08x", in_be32(&memctl->memc_mar)); in do_memcinfo()
53 printf(" MCR = %08x\n", in_be32(&memctl->memc_mcr)); in do_memcinfo()
55 in_be32(&memctl->memc_mamr), in_be32(&memctl->memc_mbmr)); in do_memcinfo()
58 in_be16(&memctl->memc_mptpr), in_be32(&memctl->memc_mdr)); in do_memcinfo()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dfsl_lsch2_serdes.c181 reg = in_be32(&serdes1_base->lane[i].gcr0); in setup_serdes_volt()
191 reg = in_be32(&serdes2_base->lane[i].gcr0); in setup_serdes_volt()
201 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
207 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
217 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
223 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
232 reg = in_be32(&serdes1_base->srdstcalcr); in setup_serdes_volt()
235 reg = in_be32(&serdes1_base->srdsrcalcr); in setup_serdes_volt()
241 reg = in_be32(&serdes2_base->srdstcalcr); in setup_serdes_volt()
244 reg = in_be32(&serdes2_base->srdsrcalcr); in setup_serdes_volt()
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dmpc8536_serdes.c94 u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS); in fsl_serdes_init()
116 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
123 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
128 tmp = in_be32(sd + FSL_SRDSCR2_OFFS); in fsl_serdes_init()
135 tmp = in_be32(sd + FSL_SRDSCR3_OFFS); in fsl_serdes_init()
144 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
149 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
154 tmp = in_be32(sd + FSL_SRDSCR2_OFFS); in fsl_serdes_init()
159 tmp = in_be32(sd + FSL_SRDSCR3_OFFS); in fsl_serdes_init()
166 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
[all …]
H A Dfsl_corenet2_serdes.c125 u32 cfg = in_be32(&gur->rcwsr[4]); in serdes_get_first_lane()
212 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; in serdes_init()
225 sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0); in serdes_init()
232 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
267 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); in serdes_init()
276 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
284 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); in serdes_init()
294 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); in serdes_init()
303 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
306 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); in serdes_init()
[all …]
H A Dqe_io.c34 in_be32(&par_io[port].cpdir2) : in qe_config_iopin()
35 in_be32(&par_io[port].cpdir1); in qe_config_iopin()
49 tmp_val = in_be32(&par_io[port].cpodr); in qe_config_iopin()
57 in_be32(&par_io[port].cppar2): in qe_config_iopin()
58 in_be32(&par_io[port].cppar1); in qe_config_iopin()
H A Dcmd_errata.c42 if (in_be32(dcsr + offsets[i]) != 2) { in check_erratum_a4849()
63 if (in_be32(dcsr + 0x108) != x108) { in check_erratum_a4849()
101 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) || in check_erratum_a4580()
102 (in_be32(&srds_lane->res4[1]) != 0x880000) || in check_erratum_a4580()
103 (in_be32(&srds_lane->res4[3]) != 0x40000044)) { in check_erratum_a4580()
125 if (in_be32(plldgdcr) & 0x1fe) { in check_erratum_a007212()
H A Dmp.c51 (void)in_be32(&pic->pir); in cpu_reset()
94 u32 coredisrl = in_be32(&gur->coredisrl); in is_core_disabled()
120 u32 devdisr = in_be32(&gur->devdisr); in is_core_disabled()
267 whoami = in_be32(&pic->whoami); in plat_mp_up()
279 in_be32(&ccm->bstrar); in plat_mp_up()
310 in_be32(&rcpm->ctbenrl); in plat_mp_up()
340 whoami = in_be32(&pic->whoami); in plat_mp_up()
344 devdisr = in_be32(&gur->devdisr); in plat_mp_up()
353 bpcr = in_be32(&ecm->eebpcr); in plat_mp_up()
386 in_be32(&gur->devdisr); in plat_mp_up()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c66 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) in clock_exit_limp()
93 temp = in_be32(&pll->pcr); in setup_5441x_clocks()
98 temp = in_be32(&pll->pdr); in setup_5441x_clocks()
107 vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) * in setup_5441x_clocks()
113 pdr = in_be32(&pll->pdr); in setup_5441x_clocks()
172 pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF; in setup_5445x_clocks()
187 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000; in setup_5445x_clocks()
189 while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK) in setup_5445x_clocks()
200 int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; in setup_5445x_clocks()
203 j = (in_be32(&pll->pcr) & 0xFF000000) >> 24; in setup_5445x_clocks()
[all …]
/rk3399_rockchip-uboot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c210 save1 = in_be32(&ddr->debug[12]); in fsl_ddr_set_memctl_regs()
211 save2 = in_be32(&ddr->debug[21]); in fsl_ddr_set_memctl_regs()
218 while (!(in_be32(&ddr->debug[1]) & 0x2)) in fsl_ddr_set_memctl_regs()
232 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
252 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
272 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
292 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
312 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
325 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) in fsl_ddr_set_memctl_regs()
347 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) in fsl_ddr_set_memctl_regs()
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/
H A Dserdes.c54 tmp = in_be32(regs + FSL_SRDSCR0_OFFS); in fsl_setup_serdes()
59 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
68 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); in fsl_setup_serdes()
81 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
86 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
104 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
109 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
126 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
131 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
148 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); in fsl_setup_serdes()
H A Dqe_io.c32 in_be32(&par_io->ioport[port].dir2) : in qe_config_iopin()
33 in_be32(&par_io->ioport[port].dir1); in qe_config_iopin()
47 tmp_val = in_be32(&par_io->ioport[port].podr); in qe_config_iopin()
56 in_be32(&par_io->ioport[port].ppar2): in qe_config_iopin()
57 in_be32(&par_io->ioport[port].ppar1); in qe_config_iopin()
/rk3399_rockchip-uboot/drivers/net/fm/
H A Dtgec_phy.c33 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_write()
44 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_write()
51 while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY) in tgec_mdio_write()
75 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_read()
86 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_read()
94 while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY) in tgec_mdio_read()
98 if (in_be32(&regs->mdio_stat) & MDIO_STAT_RD_ER) in tgec_mdio_read()
101 return in_be32(&regs->mdio_data) & 0xffff; in tgec_mdio_read()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf5227x/
H A Dspeed.c64 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) in clock_exit_limp()
79 pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF; in get_clocks()
91 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
94 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); in get_clocks()
98 ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * in get_clocks()
104 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
113 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; in get_clocks()
116 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; in get_clocks()
/rk3399_rockchip-uboot/drivers/serial/
H A Dserial_xuartlite.c44 if (in_be32(&regs->status) & SR_TX_FIFO_FULL) in uartlite_serial_putc()
57 if (!(in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA)) in uartlite_serial_getc()
60 return in_be32(&regs->rx_fifo) & 0xff; in uartlite_serial_getc()
69 return in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA; in uartlite_serial_pending()
71 return !(in_be32(&regs->status) & SR_TX_FIFO_EMPTY); in uartlite_serial_pending()
81 in_be32(&regs->control); in uartlite_serial_probe()
128 in_be32(&regs->control); in _debug_uart_init()
135 while (in_be32(&regs->status) & SR_TX_FIFO_FULL) in _debug_uart_putc()
/rk3399_rockchip-uboot/board/gdsys/common/
H A Dmiiphybb.c28 in_be32((void *)GPIO0_TCR) | pins->mdio); in io_bb_mdio_active()
38 in_be32((void *)GPIO0_TCR) & ~pins->mdio); in io_bb_mdio_tristate()
49 in_be32((void *)GPIO0_OR) | pins->mdio); in io_bb_set_mdio()
52 in_be32((void *)GPIO0_OR) & ~pins->mdio); in io_bb_set_mdio()
61 *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0); in io_bb_get_mdio()
72 in_be32((void *)GPIO0_OR) | pins->mdc); in io_bb_set_mdc()
75 in_be32((void *)GPIO0_OR) & ~pins->mdc); in io_bb_set_mdc()
/rk3399_rockchip-uboot/board/xes/common/
H A Dfsl_8xxx_pci.c30 u32 devdisr = in_be32(&gur->devdisr); in pci_init_board()
31 uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD; in pci_init_board()
32 uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; in pci_init_board()
33 uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; in pci_init_board()
34 uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1; in pci_init_board()
H A Dfsl_8xxx_clk.c22 if (in_be32(&gur->gpporcr) & 0x10000) in get_board_sys_clk()
40 u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9; in get_board_ddr_clk()
46 if (in_be32(&gur->gpporcr) & 0x20000) in get_board_ddr_clk()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc8xxx/
H A Dlaw.c38 ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) | in get_law_base_addr()
39 in_be32(LAWBARL_ADDR(idx)); in get_law_base_addr()
41 return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT; in get_law_base_addr()
64 in_be32(LAWAR_ADDR(idx)); in set_law()
75 in_be32(LAWAR_ADDR(idx)); in disable_law()
86 lawar = in_be32(LAWAR_ADDR(i)); in get_law_entry()
165 lawar = in_be32(LAWAR_ADDR(i)); in print_laws()
168 i, in_be32(LAWBARH_ADDR(i)), in print_laws()
169 i, in_be32(LAWBARL_ADDR(i))); in print_laws()
171 printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i))); in print_laws()
[all …]
H A Dsrio.c83 conf_lane = (in_be32((void *)&srds_regs->srdspccr0) in srio_erratum_a004034()
85 init_lane = (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
93 if (in_be32((void *)&srds_regs->bank[0].rstctl) in srio_erratum_a004034()
104 if (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
156 in_be32(&srds_regs->lane[idx].gcr0); in srio_erratum_a004034()
173 in_be32(&srds_regs->lane[idx].gcr0); in srio_erratum_a004034()
193 (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
195 if (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
214 if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr) in srio_erratum_a004034()
349 escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr); in srio_boot_master_release_slave()
[all …]
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf532x/
H A Dspeed.c68 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; in get_sys_clock()
69 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); in get_sys_clock()
70 u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1; in get_sys_clock()
154 u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1; in clock_pll()
155 mfd = (in_be32(&pll->pcr) & 0x3F) + 1; in clock_pll()
200 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
233 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
/rk3399_rockchip-uboot/drivers/spi/
H A Dfsl_espi.c150 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & in spi_claim_bus()
156 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
161 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
164 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
168 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
172 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
201 event = in_be32(&espi->event); in fsl_espi_tx()
230 tmpdin = in_be32(&espi->rx); in fsl_espi_rx()
319 event = in_be32(&espi->event); in spi_xfer()
329 event = in_be32(&espi->event); in spi_xfer()
[all …]
/rk3399_rockchip-uboot/drivers/net/
H A Dxilinx_ll_temac_fifo.c55 if (in_be32(&fifo_ctrl->isr) & LL_FIFO_ISR_RC) { in ll_temac_recv_fifo()
78 if (in_be32(&fifo_ctrl->rdfo) & LL_FIFO_RDFO_MASK) { in ll_temac_recv_fifo()
79 length = in_be32(&fifo_ctrl->rlf) & LL_FIFO_RLF_MASK; in ll_temac_recv_fifo()
94 *buf++ = in_be32(&fifo_ctrl->rdfd); in ll_temac_recv_fifo()
/rk3399_rockchip-uboot/board/freescale/p1_p2_rdb_pc/
H A Dspl.c34 setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); in board_init_f()
36 in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); in board_init_f()
39 in_be32(&gur->pmuxcr); in board_init_f()
46 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; in board_init_f()
/rk3399_rockchip-uboot/board/Arcturus/ucp1020/
H A Dspl.c42 setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); in board_init_f()
44 in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); in board_init_f()
47 in_be32(&gur->pmuxcr); in board_init_f()
54 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; in board_init_f()

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