freescale/p1_p2_rdb_pc/spl.c

3e6e6983SYing Zhang/*
3e6e6983SYing Zhang * Copyright 2013 Freescale Semiconductor, Inc.
3e6e6983SYing Zhang *
3e6e6983SYing Zhang * SPDX-License-Identifier:	GPL-2.0+
3e6e6983SYing Zhang */
3e6e6983SYing Zhang
3e6e6983SYing Zhang#include <common.h>
24b852a7SSimon Glass#include <console.h>
*203e94f6SSimon Glass#include <environment.h>
3e6e6983SYing Zhang#include <ns16550.h>
3e6e6983SYing Zhang#include <malloc.h>
3e6e6983SYing Zhang#include <mmc.h>
3e6e6983SYing Zhang#include <nand.h>
3e6e6983SYing Zhang#include <i2c.h>
3e6e6983SYing Zhang#include <fsl_esdhc.h>
d34e5624SYing Zhang#include <spi_flash.h>
ea022a37SSimon Glass#include "../common/spl.h"
3e6e6983SYing Zhang
3e6e6983SYing ZhangDECLARE_GLOBAL_DATA_PTR;
3e6e6983SYing Zhang
e3866163SYork Sunphys_size_t get_effective_memsize(void)
3e6e6983SYing Zhang{
3e6e6983SYing Zhang	return CONFIG_SYS_L2_SIZE;
3e6e6983SYing Zhang}
3e6e6983SYing Zhang
3e6e6983SYing Zhangvoid board_init_f(ulong bootflag)
3e6e6983SYing Zhang{
3e6e6983SYing Zhang	u32 plat_ratio, bus_clk;
3e6e6983SYing Zhang	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
3e6e6983SYing Zhang
3e6e6983SYing Zhang	console_init_f();
3e6e6983SYing Zhang
3e6e6983SYing Zhang	/* Set pmuxcr to allow both i2c1 and i2c2 */
3e6e6983SYing Zhang	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
3e6e6983SYing Zhang	setbits_be32(&gur->pmuxcr,
3e6e6983SYing Zhang		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
3e6e6983SYing Zhang
3e6e6983SYing Zhang	/* Read back the register to synchronize the write. */
3e6e6983SYing Zhang	in_be32(&gur->pmuxcr);
3e6e6983SYing Zhang
d34e5624SYing Zhang#ifdef CONFIG_SPL_SPI_BOOT
d34e5624SYing Zhang	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
d34e5624SYing Zhang#endif
d34e5624SYing Zhang
3e6e6983SYing Zhang	/* initialize selected port with appropriate baud rate */
3e6e6983SYing Zhang	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
3e6e6983SYing Zhang	plat_ratio >>= 1;
3e6e6983SYing Zhang	bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
3e6e6983SYing Zhang	gd->bus_clk = bus_clk;
3e6e6983SYing Zhang
3e6e6983SYing Zhang	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
3e6e6983SYing Zhang		     bus_clk / 16 / CONFIG_BAUDRATE);
3e6e6983SYing Zhang#ifdef CONFIG_SPL_MMC_BOOT
3e6e6983SYing Zhang	puts("\nSD boot...\n");
d34e5624SYing Zhang#elif defined(CONFIG_SPL_SPI_BOOT)
d34e5624SYing Zhang	puts("\nSPI Flash boot...\n");
3e6e6983SYing Zhang#endif
3e6e6983SYing Zhang
3e6e6983SYing Zhang	/* copy code to RAM and jump to it - this should not return */
3e6e6983SYing Zhang	/* NOTE - code has to be copied out of NAND buffer before
3e6e6983SYing Zhang	 * other blocks can be read.
3e6e6983SYing Zhang	 */
3e6e6983SYing Zhang	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
3e6e6983SYing Zhang}
3e6e6983SYing Zhang
3e6e6983SYing Zhangvoid board_init_r(gd_t *gd, ulong dest_addr)
3e6e6983SYing Zhang{
3e6e6983SYing Zhang	/* Pointer is writable since we allocated a register for it */
3e6e6983SYing Zhang	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
3e6e6983SYing Zhang	bd_t *bd;
3e6e6983SYing Zhang
3e6e6983SYing Zhang	memset(gd, 0, sizeof(gd_t));
3e6e6983SYing Zhang	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
3e6e6983SYing Zhang	memset(bd, 0, sizeof(bd_t));
3e6e6983SYing Zhang	gd->bd = bd;
3e6e6983SYing Zhang	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
3e6e6983SYing Zhang	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
3e6e6983SYing Zhang
cbcbf71bSSimon Glass	arch_cpu_init();
3e6e6983SYing Zhang	get_clocks();
3e6e6983SYing Zhang	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
3e6e6983SYing Zhang			CONFIG_SPL_RELOC_MALLOC_SIZE);
ed4708aaSSumit Garg	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
3e6e6983SYing Zhang
62c6ef33SYing Zhang#ifndef CONFIG_SPL_NAND_BOOT
3e6e6983SYing Zhang	env_init();
62c6ef33SYing Zhang#endif
3e6e6983SYing Zhang#ifdef CONFIG_SPL_MMC_BOOT
3e6e6983SYing Zhang	mmc_initialize(bd);
3e6e6983SYing Zhang#endif
3e6e6983SYing Zhang	/* relocate environment function pointers etc. */
62c6ef33SYing Zhang#ifdef CONFIG_SPL_NAND_BOOT
62c6ef33SYing Zhang	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
62c6ef33SYing Zhang			    (uchar *)CONFIG_ENV_ADDR);
62c6ef33SYing Zhang	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
*203e94f6SSimon Glass	gd->env_valid = ENV_VALID;
62c6ef33SYing Zhang#else
3e6e6983SYing Zhang	env_relocate();
62c6ef33SYing Zhang#endif
3e6e6983SYing Zhang
3e6e6983SYing Zhang#ifdef CONFIG_SYS_I2C
3e6e6983SYing Zhang	i2c_init_all();
3e6e6983SYing Zhang#else
3e6e6983SYing Zhang	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
3e6e6983SYing Zhang#endif
3e6e6983SYing Zhang
f1683aa7SSimon Glass	dram_init();
62c6ef33SYing Zhang#ifdef CONFIG_SPL_NAND_BOOT
62c6ef33SYing Zhang	puts("Tertiary program loader running in sram...");
62c6ef33SYing Zhang#else
3e6e6983SYing Zhang	puts("Second program loader running in sram...\n");
62c6ef33SYing Zhang#endif
3e6e6983SYing Zhang
3e6e6983SYing Zhang#ifdef CONFIG_SPL_MMC_BOOT
3e6e6983SYing Zhang	mmc_boot();
d34e5624SYing Zhang#elif defined(CONFIG_SPL_SPI_BOOT)
ea022a37SSimon Glass	fsl_spi_boot();
62c6ef33SYing Zhang#elif defined(CONFIG_SPL_NAND_BOOT)
62c6ef33SYing Zhang	nand_boot();
3e6e6983SYing Zhang#endif
3e6e6983SYing Zhang}