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Searched refs:if_id (Results 1 – 18 of 18) sorted by relevance

/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_training_pbs.c52 u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0; in ddr3_tip_pbs() local
61 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
62 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_pbs()
66 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_pbs()
71 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_pbs()
93 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
94 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_pbs()
95 min_adll_per_pup[if_id][pup] = in ddr3_tip_pbs()
97 pup_state[if_id][pup] = 0x3; in ddr3_tip_pbs()
98 adll_shift_lock[if_id][pup] = 1; in ddr3_tip_pbs()
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H A Dddr3_training_hw_algo.c50 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) in ddr3_tip_write_additional_odt_setting() argument
61 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting()
64 CHECK_STATUS(ddr3_tip_if_read(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting()
67 val = data_read[if_id]; in ddr3_tip_write_additional_odt_setting()
83 (dev_num, if_id, in ddr3_tip_write_additional_odt_setting()
107 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting()
111 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting()
119 int get_valid_win_rx(u32 dev_num, u32 if_id, u8 res[4]) in get_valid_win_rx() argument
132 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id, in get_valid_win_rx()
168 u32 pup = 0, if_id = 0, num_pup = 0, rep = 0; in ddr3_tip_vref() local
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H A Dddr3_training_leveling.c31 static int ddr3_tip_wl_supp_align_err_shift(u32 dev_num, u32 if_id, u32 bus_id,
33 static int ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id,
36 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id,
38 static int ddr3_tip_wl_supp_one_clk_err_shift(u32 dev_num, u32 if_id,
66 u32 bus_num, if_id, cl_val; in ddr3_tip_dynamic_read_leveling() local
97 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
98 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
99 training_result[training_stage][if_id] = TEST_SUCCESS; in ddr3_tip_dynamic_read_leveling()
101 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, in ddr3_tip_dynamic_read_leveling()
107 if_id)); in ddr3_tip_dynamic_read_leveling()
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H A Dddr3_training_centralization.c61 u32 if_id, pattern_id, bit_id; in ddr3_tip_centralization() local
84 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
85 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_centralization()
88 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_centralization()
92 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_centralization()
107 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
108 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_centralization()
112 centralization_state[if_id][bus_id] = 0; in ddr3_tip_centralization()
113 bus_end_window[mode][if_id][bus_id] = in ddr3_tip_centralization()
115 bus_start_window[mode][if_id][bus_id] = 0; in ddr3_tip_centralization()
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H A Dddr3_training.c87 u32 if_id, u32 cl_value, u32 cwl_value);
89 static int is_bus_access_done(u32 dev_num, u32 if_id,
96 u32 if_id, enum hws_ddr_freq frequency);
98 u32 if_id, enum hws_ddr_freq frequency);
182 u32 if_id, enum hws_access_type phy_access,
185 static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id);
186 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
207 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) in ddr3_tip_configure_cs() argument
214 data = (tm->interface_params[if_id].bus_width == in ddr3_tip_configure_cs()
217 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
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H A Dddr3_debug.c100 u32 if_id, reg_addr, data_value, bus_id; in ddr3_tip_reg_dump() local
107 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()
108 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_reg_dump()
111 if_id, reg_addr, read_data, in ddr3_tip_reg_dump()
113 printf("0x%x ", read_data[if_id]); in ddr3_tip_reg_dump()
121 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()
122 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_reg_dump()
128 (dev_num, if_id, in ddr3_tip_reg_dump()
139 (dev_num, if_id, in ddr3_tip_reg_dump()
327 u32 if_id = 0; in ddr3_tip_print_log() local
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H A Dddr3_training_static.c97 u32 if_id; in ddr3_tip_static_round_trip_arr_build() local
113 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_static_round_trip_arr_build()
114 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_static_round_trip_arr_build()
118 global_bus = (if_id * bus_per_interface) + bus_index; in ddr3_tip_static_round_trip_arr_build()
149 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id, in ddr3_tip_write_leveling_static_config() argument
165 dev_num, if_id, frequency, adll_period)); in ddr3_tip_write_leveling_static_config()
168 bus_start_index = if_id * bus_per_interface; in ddr3_tip_write_leveling_static_config()
189 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_write_leveling_static_config()
194 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_write_leveling_static_config()
207 u32 if_id, in ddr3_tip_read_leveling_static_config() argument
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H A Dddr3_training_ip_engine.c479 u32 if_id, enum hws_pattern pattern, in ddr3_tip_load_pattern_to_odpg() argument
489 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
495 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
502 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
508 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
518 u32 if_id, enum hws_dir direction, u32 tx_phases, in ddr3_tip_configure_odpg() argument
530 ret = ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_configure_odpg()
584 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id, in ddr3_tip_read_training_result() argument
609 (dev_num, ACCESS_TYPE_UNICAST, if_id, CS_ENABLE_REG, in ddr3_tip_read_training_result()
612 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_read_training_result()
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H A Dddr3_a38x.c198 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
257 u32 if_id, int enable) in ddr3_tip_a38x_pipe_enable() argument
267 pipe_enable_mask = (1 << interface_map[if_id].pipe); in ddr3_tip_a38x_pipe_enable()
286 u32 if_id, u32 reg_addr, u32 data_value, in ddr3_tip_a38x_if_write() argument
293 (dev_num, ACCESS_TYPE_UNICAST, if_id, reg_addr, in ddr3_tip_a38x_if_write()
311 u32 if_id, u32 reg_addr, u32 *data, u32 mask) in ddr3_tip_a38x_if_read() argument
450 u32 if_id = 0; in ddr3_a38x_update_topology_map() local
454 tm->interface_params[if_id].memory_freq = freq; in ddr3_a38x_update_topology_map()
588 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, in ddr3_tip_a38x_set_divider() argument
594 if (if_id != 0) { in ddr3_tip_a38x_set_divider()
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H A Dddr3_training_bist.c20 u32 if_id,
140 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id, in ddr3_tip_bist_read_result() argument
147 if (IS_ACTIVE(tm->if_act_mask, if_id) == 0) in ddr3_tip_bist_read_result()
151 if_id)); in ddr3_tip_bist_read_result()
152 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
157 pst_bist_result->bist_fail_high = read_data[if_id]; in ddr3_tip_bist_read_result()
158 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
163 pst_bist_result->bist_fail_low = read_data[if_id]; in ddr3_tip_bist_read_result()
165 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
170 pst_bist_result->bist_last_fail_addr = read_data[if_id]; in ddr3_tip_bist_read_result()
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H A Dddr3_training_ip_flow.h31 #define IS_ACTIVE(if_mask , if_id) \ argument
32 ((if_mask) & (1 << (if_id)))
284 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
287 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id,
291 u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
293 u32 if_id, u32 exp_value, u32 mask, u32 offset,
296 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
299 u32 if_id, u32 phy_id,
302 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access,
306 u32 if_id, enum hws_access_type e_phy_access, u32 phy_id,
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H A Dddr3_training_ip_prv_if.h26 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
29 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
39 u8 dev_num, u32 if_id, enum hws_ddr_freq freq);
48 u32 dev_num, enum hws_access_type dunit_access_type, u32 if_id,
52 u32 dev_num, u32 if_id, enum hws_access_type phy_access_type,
57 u32 dev_num, enum hws_access_type access_type, u32 if_id,
69 enum hws_static_config_type static_config_type, u32 if_id);
71 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
73 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
82 u32 dev_num, u32 if_id, struct bist_result *pst_bist_result);
H A Dddr3_training_ip_engine.h44 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
66 u32 if_id,
79 int is_odpg_access_done(u32 dev_num, u32 if_id);
H A Dddr3_training_hw_algo.h11 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id);
H A Dddr3_training_leveling.h13 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
H A Dddr3_training_ip_bist.h36 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
H A Dddr3_init.h328 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
330 u32 if_id, u32 reg_addr, u32 data, u32 mask);
359 int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
/rk3399_rockchip-uboot/include/fsl-mc/
H A Dfsl_dprc.h348 MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint1->if_id); \
350 MC_CMD_OP(cmd, 1, 32, 16, uint16_t, endpoint2->if_id); \
391 MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint->if_id); \
414 MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint1->if_id); \
437 MC_RSP_OP(cmd, 3, 32, 16, uint16_t, endpoint2->if_id); \
883 uint16_t if_id; member