1*f1df9364SStefan Roese /* 2*f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 3*f1df9364SStefan Roese * 4*f1df9364SStefan Roese * SPDX-License-Identifier: GPL-2.0 5*f1df9364SStefan Roese */ 6*f1df9364SStefan Roese 7*f1df9364SStefan Roese #ifndef _DDR3_TRAINING_LEVELING_H_ 8*f1df9364SStefan Roese #define _DDR3_TRAINING_LEVELING_H_ 9*f1df9364SStefan Roese 10*f1df9364SStefan Roese #define MAX_DQ_READ_LEVELING_DELAY 15 11*f1df9364SStefan Roese 12*f1df9364SStefan Roese int ddr3_tip_print_wl_supp_result(u32 dev_num); 13*f1df9364SStefan Roese int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs, 14*f1df9364SStefan Roese u32 *cs_mask); 15*f1df9364SStefan Roese u32 hws_ddr3_tip_max_cs_get(void); 16*f1df9364SStefan Roese 17*f1df9364SStefan Roese #endif /* _DDR3_TRAINING_LEVELING_H_ */ 18