1*f1df9364SStefan Roese /* 2*f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 3*f1df9364SStefan Roese * 4*f1df9364SStefan Roese * SPDX-License-Identifier: GPL-2.0 5*f1df9364SStefan Roese */ 6*f1df9364SStefan Roese 7*f1df9364SStefan Roese #ifndef _DDR3_TRAINING_IP_BIST_H_ 8*f1df9364SStefan Roese #define _DDR3_TRAINING_IP_BIST_H_ 9*f1df9364SStefan Roese 10*f1df9364SStefan Roese #include "ddr3_training_ip.h" 11*f1df9364SStefan Roese 12*f1df9364SStefan Roese enum hws_bist_operation { 13*f1df9364SStefan Roese BIST_STOP = 0, 14*f1df9364SStefan Roese BIST_START = 1 15*f1df9364SStefan Roese }; 16*f1df9364SStefan Roese 17*f1df9364SStefan Roese enum hws_stress_jump { 18*f1df9364SStefan Roese STRESS_NONE = 0, 19*f1df9364SStefan Roese STRESS_ENABLE = 1 20*f1df9364SStefan Roese }; 21*f1df9364SStefan Roese 22*f1df9364SStefan Roese enum hws_pattern_duration { 23*f1df9364SStefan Roese DURATION_SINGLE = 0, 24*f1df9364SStefan Roese DURATION_STOP_AT_FAIL = 1, 25*f1df9364SStefan Roese DURATION_ADDRESS = 2, 26*f1df9364SStefan Roese DURATION_CONT = 4 27*f1df9364SStefan Roese }; 28*f1df9364SStefan Roese 29*f1df9364SStefan Roese struct bist_result { 30*f1df9364SStefan Roese u32 bist_error_cnt; 31*f1df9364SStefan Roese u32 bist_fail_low; 32*f1df9364SStefan Roese u32 bist_fail_high; 33*f1df9364SStefan Roese u32 bist_last_fail_addr; 34*f1df9364SStefan Roese }; 35*f1df9364SStefan Roese 36*f1df9364SStefan Roese int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id, 37*f1df9364SStefan Roese struct bist_result *pst_bist_result); 38*f1df9364SStefan Roese int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern, 39*f1df9364SStefan Roese enum hws_access_type access_type, 40*f1df9364SStefan Roese u32 if_num, enum hws_dir direction, 41*f1df9364SStefan Roese enum hws_stress_jump addr_stress_jump, 42*f1df9364SStefan Roese enum hws_pattern_duration duration, 43*f1df9364SStefan Roese enum hws_bist_operation oper_type, 44*f1df9364SStefan Roese u32 offset, u32 cs_num, u32 pattern_addr_length); 45*f1df9364SStefan Roese int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result, 46*f1df9364SStefan Roese u32 cs_num); 47*f1df9364SStefan Roese int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction, 48*f1df9364SStefan Roese u32 mode); 49*f1df9364SStefan Roese int ddr3_tip_print_regs(u32 dev_num); 50*f1df9364SStefan Roese int ddr3_tip_reg_dump(u32 dev_num); 51*f1df9364SStefan Roese int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type, 52*f1df9364SStefan Roese u32 burst_length); 53*f1df9364SStefan Roese 54*f1df9364SStefan Roese #endif /* _DDR3_TRAINING_IP_BIST_H_ */ 55