Lines Matching refs:if_id
31 static int ddr3_tip_wl_supp_align_err_shift(u32 dev_num, u32 if_id, u32 bus_id,
33 static int ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id,
36 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id,
38 static int ddr3_tip_wl_supp_one_clk_err_shift(u32 dev_num, u32 if_id,
66 u32 bus_num, if_id, cl_val; in ddr3_tip_dynamic_read_leveling() local
97 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
98 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
99 training_result[training_stage][if_id] = TEST_SUCCESS; in ddr3_tip_dynamic_read_leveling()
101 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, in ddr3_tip_dynamic_read_leveling()
107 if_id)); in ddr3_tip_dynamic_read_leveling()
108 training_result[training_stage][if_id] = in ddr3_tip_dynamic_read_leveling()
134 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
135 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
136 if ((data_read[if_id] & (1 << 30)) == 0) { in ddr3_tip_dynamic_read_leveling()
140 if_id)); in ddr3_tip_dynamic_read_leveling()
141 training_result[training_stage][if_id] = in ddr3_tip_dynamic_read_leveling()
153 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) in ddr3_tip_dynamic_read_leveling()
154 rl_values[effective_cs][bus_num][if_id] = 0; in ddr3_tip_dynamic_read_leveling()
157 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
158 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
159 training_result[training_stage][if_id] = TEST_SUCCESS; in ddr3_tip_dynamic_read_leveling()
163 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_read_leveling()
168 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_read_leveling()
216 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
217 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
219 tm->interface_params[if_id].speed_bin_index; in ddr3_tip_dynamic_read_leveling()
225 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_read_leveling()
293 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
294 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
297 if_id, in ddr3_tip_dynamic_read_leveling()
300 data = data_read[if_id]; in ddr3_tip_dynamic_read_leveling()
324 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
325 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
334 if_id, (1 << 25), (1 << 25), in ddr3_tip_dynamic_read_leveling()
346 if_id, in ddr3_tip_dynamic_read_leveling()
351 [if_id] = (u8)data_read[if_id]; in ddr3_tip_dynamic_read_leveling()
356 training_result[training_stage][if_id] = in ddr3_tip_dynamic_read_leveling()
392 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
393 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
399 data = rl_values[effective_cs][bus_num][if_id]; in ddr3_tip_dynamic_read_leveling()
404 if_id, in ddr3_tip_dynamic_read_leveling()
416 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
417 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
420 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_read_leveling()
421 CS_ENABLE_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_read_leveling()
425 (dev_num, if_id)); in ddr3_tip_dynamic_read_leveling()
429 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
430 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
431 if (training_result[training_stage][if_id] == TEST_FAILED) in ddr3_tip_dynamic_read_leveling()
443 u32 c_cs, if_id, cs_mask = 0; in ddr3_tip_legacy_dynamic_write_leveling() local
459 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_legacy_dynamic_write_leveling()
460 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_legacy_dynamic_write_leveling()
467 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, in ddr3_tip_legacy_dynamic_write_leveling()
484 u32 c_cs, if_id, cs_mask = 0; in ddr3_tip_legacy_dynamic_read_leveling() local
505 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_legacy_dynamic_read_leveling()
506 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_legacy_dynamic_read_leveling()
508 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, in ddr3_tip_legacy_dynamic_read_leveling()
526 u32 bus_num, if_id, cl_val, bit_num; in ddr3_tip_dynamic_per_bit_read_leveling() local
541 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
542 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
546 per_bit_rl_pup_status[if_id][bus_num] = 0; in ddr3_tip_dynamic_per_bit_read_leveling()
547 data2_write[if_id][bus_num] = 0; in ddr3_tip_dynamic_per_bit_read_leveling()
550 (dev_num, if_id, ACCESS_TYPE_UNICAST, in ddr3_tip_dynamic_per_bit_read_leveling()
553 &phyreg3_arr[if_id][bus_num])); in ddr3_tip_dynamic_per_bit_read_leveling()
558 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
559 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
560 training_result[training_stage][if_id] = TEST_SUCCESS; in ddr3_tip_dynamic_per_bit_read_leveling()
564 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_per_bit_read_leveling()
565 CS_ENABLE_REG, &cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
569 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_per_bit_read_leveling()
615 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
616 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
618 tm->interface_params[if_id].speed_bin_index; in ddr3_tip_dynamic_per_bit_read_leveling()
624 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_per_bit_read_leveling()
692 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
693 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
696 if_id, in ddr3_tip_dynamic_per_bit_read_leveling()
699 data = data_read[if_id]; in ddr3_tip_dynamic_per_bit_read_leveling()
723 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
724 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
731 if (per_bit_rl_pup_status[if_id][bus_num] in ddr3_tip_dynamic_per_bit_read_leveling()
739 if_id, (1 << 25), in ddr3_tip_dynamic_per_bit_read_leveling()
756 if_id, in ddr3_tip_dynamic_per_bit_read_leveling()
764 [if_id] & in ddr3_tip_dynamic_per_bit_read_leveling()
767 [if_id] & in ddr3_tip_dynamic_per_bit_read_leveling()
776 if (data > data2_write[if_id][bus_num]) in ddr3_tip_dynamic_per_bit_read_leveling()
778 [if_id] in ddr3_tip_dynamic_per_bit_read_leveling()
784 if (data2_write[if_id][bus_num] <= in ddr3_tip_dynamic_per_bit_read_leveling()
787 per_bit_rl_pup_status[if_id] in ddr3_tip_dynamic_per_bit_read_leveling()
797 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; in ddr3_tip_dynamic_per_bit_read_leveling()
798 if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
799 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
805 if (per_bit_rl_pup_status[if_id] in ddr3_tip_dynamic_per_bit_read_leveling()
812 if_id, in ddr3_tip_dynamic_per_bit_read_leveling()
816 (phyreg3_arr[if_id] in ddr3_tip_dynamic_per_bit_read_leveling()
831 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
832 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
836 if (per_bit_rl_pup_status[if_id][bus_num] == 1) in ddr3_tip_dynamic_per_bit_read_leveling()
839 if_id, in ddr3_tip_dynamic_per_bit_read_leveling()
844 data2_write[if_id] in ddr3_tip_dynamic_per_bit_read_leveling()
865 training_result[training_stage][if_id] = TEST_FAILED; in ddr3_tip_dynamic_per_bit_read_leveling()
895 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
896 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
899 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_per_bit_read_leveling()
900 CS_ENABLE_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
904 (dev_num, if_id)); in ddr3_tip_dynamic_per_bit_read_leveling()
908 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
909 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
910 if (training_result[training_stage][if_id] == TEST_FAILED) in ddr3_tip_dynamic_per_bit_read_leveling()
917 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs, in ddr3_tip_calc_cs_mask() argument
938 all_bus_cs |= tm->interface_params[if_id]. in ddr3_tip_calc_cs_mask()
940 same_bus_cs &= tm->interface_params[if_id]. in ddr3_tip_calc_cs_mask()
944 *cs_mask &= ~tm->interface_params[if_id]. in ddr3_tip_calc_cs_mask()
959 u32 reg_data = 0, iter, if_id, bus_cnt; in ddr3_tip_dynamic_write_leveling() local
974 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
975 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
977 training_result[training_stage][if_id] = TEST_SUCCESS; in ddr3_tip_dynamic_write_leveling()
981 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_write_leveling()
986 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_write_leveling()
991 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_write_leveling()
1001 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
1002 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
1005 if_id, SDRAM_OPERATION_REG, in ddr3_tip_dynamic_write_leveling()
1010 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
1011 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
1013 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f, in ddr3_tip_dynamic_write_leveling()
1026 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
1027 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
1029 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs, in ddr3_tip_dynamic_write_leveling()
1030 &cs_mask[if_id]); in ddr3_tip_dynamic_write_leveling()
1056 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_dynamic_write_leveling()
1057 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
1061 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_write_leveling()
1073 if_id, in ddr3_tip_dynamic_write_leveling()
1080 if_id, reg_data)); in ddr3_tip_dynamic_write_leveling()
1086 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
1087 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
1090 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_write_leveling()
1101 if_id, in ddr3_tip_dynamic_write_leveling()
1104 reg_data = data_read[if_id]; in ddr3_tip_dynamic_write_leveling()
1109 if_id, reg_data)); in ddr3_tip_dynamic_write_leveling()
1123 if_id, in ddr3_tip_dynamic_write_leveling()
1127 reg_data = data_read[if_id]; in ddr3_tip_dynamic_write_leveling()
1131 if_id, bus_cnt, reg_data)); in ddr3_tip_dynamic_write_leveling()
1134 (if_id * in ddr3_tip_dynamic_write_leveling()
1141 if_id, in ddr3_tip_dynamic_write_leveling()
1150 [bus_cnt][if_id] = in ddr3_tip_dynamic_write_leveling()
1151 (u8)data_read[if_id]; in ddr3_tip_dynamic_write_leveling()
1189 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
1190 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
1198 [(if_id * in ddr3_tip_dynamic_write_leveling()
1207 [if_id]; in ddr3_tip_dynamic_write_leveling()
1221 if_id, in ddr3_tip_dynamic_write_leveling()
1238 if_id, in ddr3_tip_dynamic_write_leveling()
1242 reg_data = data_read[if_id]; in ddr3_tip_dynamic_write_leveling()
1246 if_id, bus_cnt, reg_data)); in ddr3_tip_dynamic_write_leveling()
1251 training_result[training_stage][if_id] = in ddr3_tip_dynamic_write_leveling()
1265 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
1266 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
1269 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_write_leveling()
1271 read_data_sample_delay_vals[if_id], in ddr3_tip_dynamic_write_leveling()
1276 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_write_leveling()
1278 read_data_ready_delay_vals[if_id], in ddr3_tip_dynamic_write_leveling()
1283 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_write_leveling()
1284 CS_ENABLE_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_write_leveling()
1293 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
1294 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
1295 if (training_result[training_stage][if_id] == TEST_FAILED) in ddr3_tip_dynamic_write_leveling()
1308 u32 if_id, bus_id, data, data_tmp; in ddr3_tip_dynamic_write_leveling_supp() local
1312 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling_supp()
1313 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling_supp()
1319 wr_supp_res[if_id][bus_id].is_pup_fail = 1; in ddr3_tip_dynamic_write_leveling_supp()
1321 (dev_num, if_id, ACCESS_TYPE_UNICAST, in ddr3_tip_dynamic_write_leveling_supp()
1331 (dev_num, if_id, bus_id, 0, 0) == MV_OK) { in ddr3_tip_dynamic_write_leveling_supp()
1335 if_id, bus_id)); in ddr3_tip_dynamic_write_leveling_supp()
1342 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_write_leveling_supp()
1348 (dev_num, if_id, ACCESS_TYPE_UNICAST, in ddr3_tip_dynamic_write_leveling_supp()
1359 (dev_num, if_id, bus_id, adll_offset, 0) == MV_OK) { in ddr3_tip_dynamic_write_leveling_supp()
1363 if_id, bus_id, adll_offset)); in ddr3_tip_dynamic_write_leveling_supp()
1370 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_write_leveling_supp()
1376 (dev_num, if_id, ACCESS_TYPE_UNICAST, in ddr3_tip_dynamic_write_leveling_supp()
1386 (dev_num, if_id, bus_id, adll_offset, 0) == MV_OK) { in ddr3_tip_dynamic_write_leveling_supp()
1390 if_id, bus_id, adll_offset)); in ddr3_tip_dynamic_write_leveling_supp()
1396 if_id, bus_id)); in ddr3_tip_dynamic_write_leveling_supp()
1402 if_id, bus_id, is_if_fail)); in ddr3_tip_dynamic_write_leveling_supp()
1406 ("WL Supp: IF %d failed\n", if_id)); in ddr3_tip_dynamic_write_leveling_supp()
1407 training_result[training_stage][if_id] = TEST_FAILED; in ddr3_tip_dynamic_write_leveling_supp()
1409 training_result[training_stage][if_id] = TEST_SUCCESS; in ddr3_tip_dynamic_write_leveling_supp()
1413 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling_supp()
1414 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling_supp()
1415 if (training_result[training_stage][if_id] == TEST_FAILED) in ddr3_tip_dynamic_write_leveling_supp()
1425 static int ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id, in ddr3_tip_wl_supp_align_phase_shift() argument
1429 wr_supp_res[if_id][bus_id].stage = PHASE_SHIFT; in ddr3_tip_wl_supp_align_phase_shift()
1430 if (ddr3_tip_xsb_compare_test(dev_num, if_id, bus_id, in ddr3_tip_wl_supp_align_phase_shift()
1432 wr_supp_res[if_id][bus_id].is_pup_fail = 0; in ddr3_tip_wl_supp_align_phase_shift()
1434 } else if (ddr3_tip_xsb_compare_test(dev_num, if_id, bus_id, in ddr3_tip_wl_supp_align_phase_shift()
1438 wr_supp_res[if_id][bus_id].stage = CLOCK_SHIFT; in ddr3_tip_wl_supp_align_phase_shift()
1441 if_id, bus_id, offset)); in ddr3_tip_wl_supp_align_phase_shift()
1442 ddr3_tip_wl_supp_one_clk_err_shift(dev_num, if_id, bus_id, 0); in ddr3_tip_wl_supp_align_phase_shift()
1443 wr_supp_res[if_id][bus_id].is_pup_fail = 0; in ddr3_tip_wl_supp_align_phase_shift()
1445 } else if (ddr3_tip_xsb_compare_test(dev_num, if_id, bus_id, in ddr3_tip_wl_supp_align_phase_shift()
1451 if_id, bus_id, offset)); in ddr3_tip_wl_supp_align_phase_shift()
1452 wr_supp_res[if_id][bus_id].stage = ALIGN_SHIFT; in ddr3_tip_wl_supp_align_phase_shift()
1453 ddr3_tip_wl_supp_align_err_shift(dev_num, if_id, bus_id, 0); in ddr3_tip_wl_supp_align_phase_shift()
1454 wr_supp_res[if_id][bus_id].is_pup_fail = 0; in ddr3_tip_wl_supp_align_phase_shift()
1457 wr_supp_res[if_id][bus_id].is_pup_fail = 1; in ddr3_tip_wl_supp_align_phase_shift()
1465 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id, in ddr3_tip_xsb_compare_test() argument
1481 (dev_num, if_id, in ddr3_tip_xsb_compare_test()
1489 (dev_num, if_id, in ddr3_tip_xsb_compare_test()
1496 if_id, bus_id, read_pattern[0], read_pattern[1], in ddr3_tip_xsb_compare_test()
1521 if_id, bus_id, num_of_succ_byte_compare)); in ddr3_tip_xsb_compare_test()
1527 if_id, bus_id, num_of_succ_byte_compare)); in ddr3_tip_xsb_compare_test()
1551 if_id, bus_id, num_of_succ_byte_compare)); in ddr3_tip_xsb_compare_test()
1560 static int ddr3_tip_wl_supp_one_clk_err_shift(u32 dev_num, u32 if_id, in ddr3_tip_wl_supp_one_clk_err_shift() argument
1568 (dev_num, if_id, ACCESS_TYPE_UNICAST, bus_id, in ddr3_tip_wl_supp_one_clk_err_shift()
1574 if_id, bus_id, phase, adll)); in ddr3_tip_wl_supp_one_clk_err_shift()
1578 (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_id, in ddr3_tip_wl_supp_one_clk_err_shift()
1584 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_wl_supp_one_clk_err_shift()
1589 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_wl_supp_one_clk_err_shift()
1603 static int ddr3_tip_wl_supp_align_err_shift(u32 dev_num, u32 if_id, in ddr3_tip_wl_supp_align_err_shift() argument
1610 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id, ACCESS_TYPE_UNICAST, in ddr3_tip_wl_supp_align_err_shift()
1618 if_id, bus_id, phase, adll)); in ddr3_tip_wl_supp_align_err_shift()
1629 if_id, bus_id, DDR_PHY_DATA, in ddr3_tip_wl_supp_align_err_shift()
1634 if_id, bus_id, DDR_PHY_DATA, in ddr3_tip_wl_supp_align_err_shift()
1645 (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_id, in ddr3_tip_wl_supp_align_err_shift()
1804 u32 bus_id = 0, if_id = 0; in ddr3_tip_print_wl_supp_result() local
1810 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_print_wl_supp_result()
1811 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_print_wl_supp_result()
1816 ("%d ,", wr_supp_res[if_id] in ddr3_tip_print_wl_supp_result()
1824 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_print_wl_supp_result()
1825 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_print_wl_supp_result()
1830 ("%d ,", wr_supp_res[if_id] in ddr3_tip_print_wl_supp_result()